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Message-ID: <20220818035956.1160585-3-neal_liu@aspeedtech.com>
Date: Thu, 18 Aug 2022 11:59:53 +0800
From: Neal Liu <neal_liu@...eedtech.com>
To: Corentin Labbe <clabbe.montjoie@...il.com>,
Christophe JAILLET <christophe.jaillet@...adoo.fr>,
Randy Dunlap <rdunlap@...radead.org>,
Herbert Xu <herbert@...dor.apana.org.au>,
"David S . Miller" <davem@...emloft.net>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Joel Stanley <joel@....id.au>,
"Andrew Jeffery" <andrew@...id.au>,
Dhananjay Phadke <dhphadke@...rosoft.com>,
"Johnny Huang" <johnny_huang@...eedtech.com>
CC: <linux-aspeed@...ts.ozlabs.org>, <linux-crypto@...r.kernel.org>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <BMC-SW@...eedtech.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH v10 2/5] dt-bindings: clock: Add AST2500/AST2600 HACE reset definition
Add HACE reset bit definition for AST2500/AST2600.
Signed-off-by: Neal Liu <neal_liu@...eedtech.com>
Signed-off-by: Johnny Huang <johnny_huang@...eedtech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
include/dt-bindings/clock/aspeed-clock.h | 1 +
include/dt-bindings/clock/ast2600-clock.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index 9ff4f6e4558c..06d568382c77 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -52,5 +52,6 @@
#define ASPEED_RESET_I2C 7
#define ASPEED_RESET_AHB 8
#define ASPEED_RESET_CRT1 9
+#define ASPEED_RESET_HACE 10
#endif
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
index 62b9520a00fd..d8b0db2f7a7d 100644
--- a/include/dt-bindings/clock/ast2600-clock.h
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -111,6 +111,7 @@
#define ASPEED_RESET_PCIE_RC_O 19
#define ASPEED_RESET_PCIE_RC_OEN 18
#define ASPEED_RESET_PCI_DP 5
+#define ASPEED_RESET_HACE 4
#define ASPEED_RESET_AHB 1
#define ASPEED_RESET_SDRAM 0
--
2.25.1
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