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Message-ID: <875yiptvsc.fsf@redhat.com>
Date: Thu, 18 Aug 2022 17:29:23 +0200
From: Vitaly Kuznetsov <vkuznets@...hat.com>
To: Sean Christopherson <seanjc@...gle.com>
Cc: kvm@...r.kernel.org, Paolo Bonzini <pbonzini@...hat.com>,
Anirudh Rayabharam <anrayabh@...ux.microsoft.com>,
Wanpeng Li <wanpengli@...cent.com>,
Jim Mattson <jmattson@...gle.com>,
Maxim Levitsky <mlevitsk@...hat.com>,
Nathan Chancellor <nathan@...nel.org>,
Michael Kelley <mikelley@...rosoft.com>,
linux-hyperv@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 03/26] x86/hyperv: Update 'struct
hv_enlightened_vmcs' definition
Sean Christopherson <seanjc@...gle.com> writes:
> On Tue, Aug 02, 2022, Vitaly Kuznetsov wrote:
>> Updated Hyper-V Enlightened VMCS specification lists several new
>> fields for the following features:
>>
>> - PerfGlobalCtrl
>> - EnclsExitingBitmap
>> - Tsc Scaling
>> - GuestLbrCtl
>> - CET
>> - SSP
>>
>> Update the definition. The updated definition is available only when
>> CPUID.0x4000000A.EBX BIT(0) is '1'. Add a define for it as well.
>>
>> Note: The latest TLFS is available at
>> https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/tlfs
>>
>> Reviewed-by: Maxim Levitsky <mlevitsk@...hat.com>
>> Signed-off-by: Vitaly Kuznetsov <vkuznets@...hat.com>
>> ---
>> arch/x86/include/asm/hyperv-tlfs.h | 26 ++++++++++++++++++++++++--
>> 1 file changed, 24 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h
>> index 6f0acc45e67a..ebc27017fa48 100644
>> --- a/arch/x86/include/asm/hyperv-tlfs.h
>> +++ b/arch/x86/include/asm/hyperv-tlfs.h
>> @@ -138,6 +138,17 @@
>> #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18)
>> #define HV_X64_NESTED_MSR_BITMAP BIT(19)
>>
>> +/*
>> + * Nested quirks. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits.
>
> The "quirks" part is very confusing, largely because KVM has a well-established
> quirks mechanism. I also don't see "quirks" anywhere in the TLFS documentation.
> Can the "Nested quirks" part simply be dropped?
>
Yes, it's completely made up (just like I made up
HV_X64_NESTED_EVMCS1_2022_UPDATE), let's drop it.
>> + *
>> + * Note: HV_X64_NESTED_EVMCS1_2022_UPDATE is not currently documented in any
>> + * published TLFS version. When the bit is set, nested hypervisor can use
>> + * 'updated' eVMCSv1 specification (perf_global_ctrl, s_cet, ssp, lbr_ctl,
>> + * encls_exiting_bitmap, tsc_multiplier fields which were missing in 2016
>> + * specification).
>> + */
>> +#define HV_X64_NESTED_EVMCS1_2022_UPDATE BIT(0)
>
> This bit is now defined[*], but the docs says it's only for perf_global_ctrl. Are
> we expecting an update to the TLFS?
>
> Indicates support for the GuestPerfGlobalCtrl and HostPerfGlobalCtrl fields
> in the enlightened VMCS.
>
> [*] https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/feature-discovery#hypervisor-nested-virtualization-features---0x4000000a
>
Oh well, better this than nothing. I'll ping the people who told me
about this bit that their description is incomplete.
>> +
>> /*
>> * This is specific to AMD and specifies that enlightened TLB flush is
>> * supported. If guest opts in to this feature, ASID invalidations only
>> @@ -559,9 +570,20 @@ struct hv_enlightened_vmcs {
>> u64 partition_assist_page;
>> u64 padding64_4[4];
>> u64 guest_bndcfgs;
>> - u64 padding64_5[7];
>> + u64 guest_ia32_perf_global_ctrl;
>> + u64 guest_ia32_s_cet;
>> + u64 guest_ssp;
>> + u64 guest_ia32_int_ssp_table_addr;
>> + u64 guest_ia32_lbr_ctl;
>> + u64 padding64_5[2];
>> u64 xss_exit_bitmap;
>> - u64 padding64_6[7];
>> + u64 encls_exiting_bitmap;
>> + u64 host_ia32_perf_global_ctrl;
>> + u64 tsc_multiplier;
>> + u64 host_ia32_s_cet;
>> + u64 host_ssp;
>> + u64 host_ia32_int_ssp_table_addr;
>> + u64 padding64_6;
>> } __packed;
>>
>> #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0
>> --
>> 2.35.3
>>
>
--
Vitaly
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