Date:   Thu, 18 Aug 2022 15:34:08 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <robh@...nel.org>, <mail@...chuod.ie>
CC:     <Daire.McNamara@...rochip.com>, <bhelgaas@...gle.com>,
        <krzysztof.kozlowski+dt@...aro.org>, <paul.walmsley@...ive.com>,
        <greentime.hu@...ive.com>, <palmer@...belt.com>,
        <aou@...s.berkeley.edu>, <lpieralisi@...nel.org>,
        <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH v2 2/6] dt-bindings: PCI: microchip,pcie-host: fix missing
 clocks properties

On 18/08/2022 16:06, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Tue, Aug 16, 2022 at 07:25:44PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@...rochip.com>
>>
>> Recent versions of dt-schema warn about unevaluatedProperties:
>> arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@...0000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected)
>>         From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
>>
>> The clocks are required to enable interfaces between the FPGA fabric
>> and the core complex, so add them to the binding.
>>
>> Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding")
>> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
>> ---
>> dt-schema v2022.08 is required to replicate
>> ---
>>  .../bindings/pci/microchip,pcie-host.yaml     | 25 +++++++++++++++++++
>>  1 file changed, 25 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
>> index edb4f81253c8..6bbde8693ef8 100644
>> --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
>> +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
>> @@ -25,6 +25,31 @@ properties:
>>        - const: cfg
>>        - const: apb
>>
>> +  clocks:
>> +    description:
>> +      Fabric Interface Controllers, FICs, are the interface between the FPGA
>> +      fabric and the core complex on PolarFire SoC. The FICs require two clocks,
>> +      one from each side of the interface. The "FIC clocks" described by this
>> +      property are on the core complex side & communication through a FIC is not
>> +      possible unless it's corresponding clock is enabled. A clock must be
>> +      enabled for each of the interfaces the root port is connected through.
>> +      This could in theory be all 4 interfaces, one interface or any combination
>> +      in between.
>> +    minItems: 1
>> +    items:
>> +      - description: FIC0's clock
>> +      - description: FIC1's clock
>> +      - description: FIC2's clock
>> +      - description: FIC3's clock
>> +
>> +  clock-names:
>> +    description:
>> +      As any FIC connection combination is possible, the names should match the
>> +      order in the clocks property and take the form "ficN" where N is a number
>> +      0-3
>> +    minItems: 1
>> +    maxItems: 4
> 
> items:
>   pattern: '^fic[0-3]$'

I'm glad you wrote this one for me Rob!
I'll send another version next week.
Thanks,
Conor.

> 
>> +
>>    interrupts:
>>      minItems: 1
>>      items:
>> --
>> 2.37.1
>>
>>
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