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Message-ID: <20220818163648.GD1978870-robh@kernel.org>
Date: Thu, 18 Aug 2022 10:36:48 -0600
From: Rob Herring <robh@...nel.org>
To: Conor Dooley <mail@...chuod.ie>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Anup Patel <anup@...infault.org>,
Conor Dooley <conor.dooley@...rochip.com>,
Guo Ren <guoren@...nel.org>,
Sagar Kadam <sagar.kadam@...ive.com>,
Jessica Clarke <jrtc27@...c27.com>,
Andrew Jones <ajones@...tanamicro.com>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, qemu-riscv@...gnu.org
Subject: Re: [PATCH v3 2/4] dt-bindings: interrupt-controller: sifive,plic:
add legacy riscv compatible
On Wed, Aug 17, 2022 at 09:12:11PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
>
> While "real" hardware might not use the compatible string "riscv,plic0"
> it is present in the driver & QEMU uses it for automatically generated
> virt machine dtbs. To avoid dt-validate problems with QEMU produced
> dtbs, such as the following, add it to the binding.
>
> riscv-virt.dtb: plic@...0000: compatible: 'oneOf' conditional failed, one must be fixed:
> 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic']
> 'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic']
> 'sifive,plic-1.0.0' was expected
> 'thead,c900-plic' was expected
> riscv-virt.dtb: plic@...0000: '#address-cells' is a required property
>
> Reported-by: Rob Herring <robh@...nel.org>
> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
> .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Rob Herring <robh@...nel.org>
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