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Message-ID: <0976b1c1-a8e0-5a61-51ff-9b47f29569a5@linaro.org>
Date: Fri, 19 Aug 2022 15:45:09 +0300
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Conor Dooley <conor.dooley@...rochip.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Palmer Dabbelt <palmer@...belt.com>,
Daire McNamara <daire.mcnamara@...rochip.com>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org
Subject: Re: [PATCH 2/6] dt-bindings: clk: document PolarFire SoC fabric
clocks
On 19/08/2022 15:22, Conor Dooley wrote:
> On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the
> ordinal corners of the chip, which our documentation refers to as
> "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are
> highly configurable & many of the input clocks are optional.
>
Thank you for your patch. There is something to discuss/improve.
> + '#clock-cells':
> + const: 1
> + description: |
> + The clock consumer should specify the desired clock by having the clock
> + ID in its "clocks" phandle cell.
> + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
> + PolarFire clock IDs.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + ccc_nw: cccnwclk@...00000 {
Node names should be generic: clock-controller
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Best regards,
Krzysztof
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