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Message-ID: <0374171f3784ff91fc81f760ef8f81669e1099f9.camel@icenowy.me>
Date: Sun, 21 Aug 2022 15:06:46 +0800
From: Icenowy Zheng <uwu@...nowy.me>
To: Conor.Dooley@...rochip.com, samuel@...lland.org, wens@...e.org,
jernej.skrabec@...il.com, linux-sunxi@...ts.linux.dev,
palmer@...belt.com, paul.walmsley@...ive.com,
aou@...s.berkeley.edu, linux-riscv@...ts.infradead.org
Cc: robh+dt@...nel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, krzysztof.kozlowski+dt@...aro.org,
heiko@...ech.de
Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha
devicetree
在 2022-08-19星期五的 22:10 +0000，Conor.Dooley@...rochip.com写道：
> Hey Samuel,
>
> Finally got around to giving this a go with the fix for loading
> modules which is mostly what was blocking me before..
>
> On 15/08/2022 06:08, Samuel Holland wrote:
> > "D1 Nezha" is Allwinner's first-party development board for the D1
> > SoC.
> > It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard
> > audio,
BTW I assume 512MB version is never publicly available, it's only some
early samples that have the circuit of one of the DDR chips broken.
>
> I am really not keen on the way you have things, with the memory
> nodes removed from the device tree. I know your preferred flow
> for booting these things might be to pass the dtb up from U-Boot,
> but I think the devicetree in the kernel should be usable in a
> standalone manner, even if that is the barest-minimum memory
> config.
W/o interception of BL, I think there're more complex situations of the
memory, e.g. some part of the memory is reserved.
>
> I did figure out all of my issues getting booted, thanks partly
> to Heiko. The U-Boot dtb being misaligned was part of it as was
> my initramfs with some stale sunxi modules in it causing RCU
> stalls.. so sorry for the noise on that front (and thanks again
> to Heiko!).
>
> Modulo the memory node, since I had to hack that in to get things
> working & I do not want to have to keep doing:
> Tested-by: Conor Dooley <conor.dooley@...rochip.com>
>
> Thanks & apologies again for the modules-related issues - it was
> hard to debug that one since module loading was broken on RISC-V
> at the time.
> Conor.
>
> > HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG
> > ports,
> > plus low-speed I/O from the SoC and a GPIO expander chip.
> >
> > Most other D1 boards copied the Nezha's power tree, with the 1.8V
> > rail
> > powered by the SoCs internal LDOA, analog domains powered by ALDO,
> > and
> > the rest of the board powered by always-on fixed regulators. Some
> > (but
> > not all) boards also copied the PWM CPU regulator. To avoid
> > duplication,
> > factor out the out the regulator references that are common across
> > all
> > known boards.
> >
> > Signed-off-by: Samuel Holland <samuel@...lland.org>
> > ---
> >
> > arch/riscv/boot/dts/allwinner/Makefile | 1 +
> > .../sun20i-d1-common-regulators.dtsi | 51 ++++++
> > .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171
> > ++++++++++++++++++
> > 3 files changed, 223 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-
> > regulators.dtsi
> > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-
> > nezha.dts
> >
> > diff --git a/arch/riscv/boot/dts/allwinner/Makefile
> > b/arch/riscv/boot/dts/allwinner/Makefile
> > index f66554cd5c45..b0a15e8c8d82 100644
> > --- a/arch/riscv/boot/dts/allwinner/Makefile
> > +++ b/arch/riscv/boot/dts/allwinner/Makefile
> > @@ -1 +1,2 @@
> > # SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
> > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-
> > regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-
> > regulators.dtsi
> > new file mode 100644
> > index 000000000000..143a3e710c3c
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-
> > regulators.dtsi
> > @@ -0,0 +1,51 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +// Copyright (C) 2021-2022 Samuel Holland <samuel@...lland.org>
> > +
> > +/ {
> > + reg_vcc: vcc {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + };
> > +
> > + reg_vcc_3v3: vcc-3v3 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc-3v3";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + vin-supply = <®_vcc>;
> > + };
> > +};
> > +
> > +&lradc {
> > + vref-supply = <®_aldo>;
> > +};
> > +
> > +&pio {
> > + vcc-pb-supply = <®_vcc_3v3>;
> > + vcc-pc-supply = <®_vcc_3v3>;
> > + vcc-pd-supply = <®_vcc_3v3>;
> > + vcc-pe-supply = <®_vcc_3v3>;
> > + vcc-pf-supply = <®_vcc_3v3>;
> > + vcc-pg-supply = <®_vcc_3v3>;
> > +};
> > +
> > +®_aldo {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + vdd33-supply = <®_vcc_3v3>;
> > +};
> > +
> > +®_hpldo {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + hpldoin-supply = <®_vcc_3v3>;
> > +};
> > +
> > +®_ldoa {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + ldo-in-supply = <®_vcc_3v3>;
> > +};
> > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> > b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> > new file mode 100644
> > index 000000000000..df865ee15fcf
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> > @@ -0,0 +1,171 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +// Copyright (C) 2021-2022 Samuel Holland <samuel@...lland.org>
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/input/input.h>
> > +
> > +#include "sun20i-d1.dtsi"
> > +#include "sun20i-d1-common-regulators.dtsi"
> > +
> > +/ {
> > + model = "Allwinner D1 Nezha";
> > + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
> > +
> > + aliases {
> > + ethernet0 = &emac;
> > + ethernet1 = &xr829;
> > + mmc0 = &mmc0;
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +
> > + reg_usbvbus: usbvbus {
> > + compatible = "regulator-fixed";
> > + regulator-name = "usbvbus";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
> > + enable-active-high;
> > + vin-supply = <®_vcc>;
> > + };
> > +
> > + /*
> > + * This regulator is PWM-controlled, but the PWM controller
> > is not
> > + * yet supported, so fix the regulator to its default
> > voltage.
> > + */
> > + reg_vdd_cpu: vdd-cpu {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vdd-cpu";
> > + regulator-min-microvolt = <1100000>;
> > + regulator-max-microvolt = <1100000>;
> > + vin-supply = <®_vcc>;
> > + };
> > +
> > + wifi_pwrseq: wifi-pwrseq {
> > + compatible = "mmc-pwrseq-simple";
> > + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12
> > */
> > + };
> > +};
> > +
> > +&cpu0 {
> > + cpu-supply = <®_vdd_cpu>;
> > +};
> > +
> > +&ehci0 {
> > + status = "okay";
> > +};
> > +
> > +&ehci1 {
> > + status = "okay";
> > +};
> > +
> > +&emac {
> > + pinctrl-0 = <&rgmii_pe_pins>;
> > + pinctrl-names = "default";
> > + phy-handle = <&ext_rgmii_phy>;
> > + phy-mode = "rgmii-id";
> > + phy-supply = <®_vcc_3v3>;
> > + status = "okay";
> > +};
> > +
> > +&i2c2 {
> > + pinctrl-0 = <&i2c2_pb0_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +
> > + pcf8574a: gpio@38 {
> > + compatible = "nxp,pcf8574a";
> > + reg = <0x38>;
> > + interrupt-parent = <&pio>;
> > + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
> > + interrupt-controller;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + #interrupt-cells = <2>;
> > + };
> > +};
> > +
> > +&lradc {
> > + status = "okay";
> > +
> > + button-160 {
> > + label = "OK";
> > + linux,code = <KEY_OK>;
> > + channel = <0>;
> > + voltage = <160000>;
> > + };
> > +};
> > +
> > +&mdio {
> > + ext_rgmii_phy: ethernet-phy@1 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <1>;
> > + };
> > +};
> > +
> > +&mmc0 {
> > + bus-width = <4>;
> > + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> > + disable-wp;
> > + vmmc-supply = <®_vcc_3v3>;
> > + vqmmc-supply = <®_vcc_3v3>;
> > + pinctrl-0 = <&mmc0_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +};
> > +
> > +&mmc1 {
> > + bus-width = <4>;
> > + mmc-pwrseq = <&wifi_pwrseq>;
> > + non-removable;
> > + vmmc-supply = <®_vcc_3v3>;
> > + vqmmc-supply = <®_vcc_3v3>;
> > + pinctrl-0 = <&mmc1_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +
> > + xr829: wifi@1 {
> > + reg = <1>;
> > + };
> > +};
> > +
> > +&ohci0 {
> > + status = "okay";
> > +};
> > +
> > +&ohci1 {
> > + status = "okay";
> > +};
> > +
> > +&uart0 {
> > + pinctrl-0 = <&uart0_pb8_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +};
> > +
> > +&uart1 {
> > + uart-has-rtscts;
> > + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +
> > + /* XR829 bluetooth is connected here */
> > +};
> > +
> > +&usb_otg {
> > + dr_mode = "otg";
> > + status = "okay";
> > +};
> > +
> > +&usbphy {
> > + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21
> > */
> > + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20
> > */
> > + usb0_vbus-supply = <®_usbvbus>;
> > + usb1_vbus-supply = <®_vcc>;
> > + status = "okay";
> > +};
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