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Date: Mon, 22 Aug 2022 22:14:16 +0300 From: Serge Semin <Sergey.Semin@...kalelectronics.ru> To: Michal Simek <michal.simek@...inx.com>, Borislav Petkov <bp@...en8.de>, Mauro Carvalho Chehab <mchehab@...nel.org>, Tony Luck <tony.luck@...el.com>, James Morse <james.morse@....com>, Robert Richter <rric@...nel.org> CC: Serge Semin <Sergey.Semin@...kalelectronics.ru>, Serge Semin <fancer.lancer@...il.com>, Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>, Michail Ivanov <Michail.Ivanov@...kalelectronics.ru>, Pavel Parkhomenko <Pavel.Parkhomenko@...kalelectronics.ru>, Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@...inx.com>, Manish Narani <manish.narani@...inx.com>, Dinh Nguyen <dinguyen@...nel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-edac@...r.kernel.org>, <linux-kernel@...r.kernel.org> Subject: [PATCH 07/18] EDAC/synopsys: Parse ADDRMAP[7-8] CSRs for (LP)DDR4 only These CSRs contain the SDRAM Bank Groups and row[16]/row[17] bits mapping, which are applicable for the DDR4 and LPDDR4 memory only. For the rest of the memories the ADDRMAP[7-8] are unused by the controller and may be read as garbage (for instance, return an outcome of the previous read operation). The retrieved values might be perceived by the HIF/SDRAM mapping detection procedure as normal bit positions, which is wrong. So let's parse these registers only if they are applicable for the detected DDR protocol. Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru> --- drivers/edac/synopsys_edac.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index b6296bbd1a45..998600670c75 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -1005,12 +1005,15 @@ static void snps_setup_row_address_map(struct snps_edac_priv *priv, u32 *addrmap priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) == ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) + ROW_B15_BASE); - priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) == - ROW_MAX_VAL_MASK) ? 0 : ((addrmap[7] & - ROW_MAX_VAL_MASK) + ROW_B16_BASE); - priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) == - ROW_MAX_VAL_MASK) ? 0 : (((addrmap[7] >> 8) & - ROW_MAX_VAL_MASK) + ROW_B17_BASE); + + if (priv->info.sdram_mode == MEM_DDR4 || priv->info.sdram_mode == MEM_LPDDR4) { + priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) == + ROW_MAX_VAL_MASK) ? 0 : ((addrmap[7] & + ROW_MAX_VAL_MASK) + ROW_B16_BASE); + priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) == + ROW_MAX_VAL_MASK) ? 0 : (((addrmap[7] >> 8) & + ROW_MAX_VAL_MASK) + ROW_B17_BASE); + } } static void snps_setup_column_address_map(struct snps_edac_priv *priv, u32 *addrmap) @@ -1126,6 +1129,10 @@ static void snps_setup_bank_address_map(struct snps_edac_priv *priv, u32 *addrma static void snps_setup_bg_address_map(struct snps_edac_priv *priv, u32 *addrmap) { + /* Bank group signals are available on the DDR4 memory only */ + if (priv->info.sdram_mode != MEM_DDR4) + return; + priv->bankgrp_shift[0] = (addrmap[8] & BANKGRP_MAX_VAL_MASK) + BANKGRP_B0_BASE; priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) == -- 2.35.1
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