linux-kernel - [tip: perf/urgent] perf/x86/intel/ds: Fix precise store latency handling

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Message-ID: <166115885066.401.15226681508594972592.tip-bot2@tip-bot2>
Date:   Mon, 22 Aug 2022 09:00:50 -0000
From:   "tip-bot2 for Stephane Eranian" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Stephane Eranian <eranian@...gle.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: [tip: perf/urgent] perf/x86/intel/ds: Fix precise store latency handling

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     d4bdb0bebc5ba3299d74f123c782d99cd4e25c49
Gitweb:        https://git.kernel.org/tip/d4bdb0bebc5ba3299d74f123c782d99cd4e25c49
Author:        Stephane Eranian <eranian@...gle.com>
AuthorDate:    Wed, 17 Aug 2022 22:46:13 -07:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Fri, 19 Aug 2022 19:47:31 +02:00

perf/x86/intel/ds: Fix precise store latency handling

With the existing code in store_latency_data(), the memory operation (mem_op)
returned to the user is always OP_LOAD where in fact, it should be OP_STORE.
This comes from the fact that the function is simply grabbing the information
from a data source map which covers only load accesses. Intel 12th gen CPU
offers precise store sampling that captures both the data source and latency.
Therefore it can use the data source mapping table but must override the
memory operation to reflect stores instead of loads.

Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Stephane Eranian <eranian@...gle.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Link: https://lkml.kernel.org/r/20220818054613.1548130-1-eranian@google.com
---
 arch/x86/events/intel/ds.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index ac6dd4c..e5b5874 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -291,6 +291,7 @@ static u64 load_latency_data(struct perf_event *event, u64 status)
 static u64 store_latency_data(struct perf_event *event, u64 status)
 {
 	union intel_x86_pebs_dse dse;
+	union perf_mem_data_src src;
 	u64 val;
 
 	dse.val = status;
@@ -304,7 +305,14 @@ static u64 store_latency_data(struct perf_event *event, u64 status)
 
 	val |= P(BLK, NA);
 
-	return val;
+	/*
+	 * the pebs_data_source table is only for loads
+	 * so override the mem_op to say STORE instead
+	 */
+	src.val = val;
+	src.mem_op = P(OP,STORE);
+
+	return src.val;
 }
 
 struct pebs_record_core {