linux-kernel - [tip: perf/urgent] perf/x86/intel: Fix pebs event constraints for ADL

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Message-ID: <166115884946.401.5531726230002276797.tip-bot2@tip-bot2>
Date:   Mon, 22 Aug 2022 09:00:49 -0000
From:   "tip-bot2 for Kan Liang" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Ammy Yi <ammy.yi@...el.com>, Kan Liang <kan.liang@...ux.intel.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>,
        stable@...r.kernel.org, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: [tip: perf/urgent] perf/x86/intel: Fix pebs event constraints for ADL

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     cde643ff75bc20c538dfae787ca3b587bab16b50
Gitweb:        https://git.kernel.org/tip/cde643ff75bc20c538dfae787ca3b587bab16b50
Author:        Kan Liang <kan.liang@...ux.intel.com>
AuthorDate:    Thu, 18 Aug 2022 11:44:29 -07:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Fri, 19 Aug 2022 19:47:31 +02:00

perf/x86/intel: Fix pebs event constraints for ADL

According to the latest event list, the LOAD_LATENCY PEBS event only
works on the GP counter 0 and 1 for ADL and RPL.

Update the pebs event constraints table.

Fixes: f83d2f91d259 ("perf/x86/intel: Add Alder Lake Hybrid support")
Reported-by: Ammy Yi <ammy.yi@...el.com>
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Cc: stable@...r.kernel.org
Link: https://lkml.kernel.org/r/20220818184429.2355857-1-kan.liang@linux.intel.com
---
 arch/x86/events/intel/ds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index e5b5874..de1f55d 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -830,7 +830,7 @@ struct event_constraint intel_glm_pebs_event_constraints[] = {
 
 struct event_constraint intel_grt_pebs_event_constraints[] = {
 	/* Allow all events as PEBS with no flags */
-	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xf),
+	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
 	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf),
 	EVENT_CONSTRAINT_END
 };