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Message-ID: <c09ba37c-f685-15a3-3042-8cb3a0f91282@linux.intel.com>
Date: Mon, 22 Aug 2022 17:08:55 +0200
From: Andi Kleen <ak@...ux.intel.com>
To: Peter Zijlstra <peterz@...radead.org>,
"Liang, Kan" <kan.liang@...ux.intel.com>
Cc: acme@...hat.com, linux-kernel@...r.kernel.org,
alexander.shishkin@...ux.intel.com,
Jianfeng Gao <jianfeng.gao@...el.com>,
Andrew Cooper <Andrew.Cooper3@...rix.com>
Subject: Re: [RESEND PATCH] perf/x86/intel: Fix unchecked MSR access error for
Alder Lake N
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 2db93498ff71..232e24324fd7 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -4473,6 +4473,11 @@ static bool init_hybrid_pmu(int cpu)
> struct x86_hybrid_pmu *pmu = NULL;
> int i;
>
> + if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
> + pr_warn_once("hybrid PMU and virt are incompatible\n");
> + return false;
> + }
It's totally possible to virtualize hybrid correctly, so I don't think
this is justified
-Andi
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