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Date: Mon, 22 Aug 2022 23:10:38 +0800
From: moudy ho <moudy.ho@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Hans Verkuil <hverkuil-cisco@...all.nl>
CC: Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Rob Landley <rob@...dley.net>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
<linux-media@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
Alexandre Courbot <acourbot@...omium.org>,
<tfiga@...omium.org>, <drinkcat@...omium.org>,
<pihsun@...omium.org>, <hsinyi@...gle.com>,
Benjamin Gaignard <benjamin.gaignard@...labora.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
<cellopoint.kai@...il.com>
Subject: Re: [PATCH v25 1/4] dt-binding: mediatek: add bindings for MediaTek
MDP3 components
Hi Matthias,
On Mon, 2022-08-22 at 16:31 +0200, Matthias Brugger wrote:
>
> On 17/08/2022 11:56, Moudy Ho wrote:
> > This patch adds DT binding documents for Media Data Path 3 (MDP3)
> > a unit in multimedia system combined with several components and
> > used for scaling and color format convert.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@...iatek.com>
> > Reviewed-by: Rob Herring <robh@...nel.org>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@...labora.com>
> > ---
> > .../bindings/media/mediatek,mdp3-rdma.yaml | 95
> > +++++++++++++++++++
> > .../bindings/media/mediatek,mdp3-rsz.yaml | 77
> > +++++++++++++++
> > .../bindings/media/mediatek,mdp3-wrot.yaml | 80
> > ++++++++++++++++
> > 3 files changed, 252 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml
> > new file mode 100644
> > index 000000000000..94ff74d9c04a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml
> > @@ -0,0 +1,95 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8Q2Znasv$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8RCccQrB$
> >
> > +
> > +title: MediaTek Read Direct Memory Access
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@...il.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@...iatek.com>
>
> Ping-Hsun Wu isn't even CCed on this mail. Why aren't you the
> maintainer if you
> submit the patch?
>
> Regards,
> Matthias
>
Thank you for your attention to this matter and apologies for the wrong
candidate. I'll relist the correct maintainers and release a new
version for it.
Regards,
Moudy
> > +
> > +description: |
> > + MediaTek Read Direct Memory Access(RDMA) component used to do
> > read DMA.
> > + It contains one line buffer to store the sufficient pixel data,
> > and
> > + must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.ya
> > ml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: mediatek,mt8183-mdp3-rdma
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + mediatek,gce-events:
> > + description:
> > + The event id which is mapping to the specific hardware event
> > signal
> > + to gce. The event id is defined in the gce header
> > + include/dt-bindings/gce/<chip>-gce.h of each chips.
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: RDMA clock
> > + - description: RSZ clock
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > + mboxes:
> > + items:
> > + - description: used for 1st data pipe from RDMA
> > + - description: used for 2nd data pipe from RDMA
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - mediatek,gce-events
> > + - power-domains
> > + - clocks
> > + - iommus
> > + - mboxes
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > + #include <dt-bindings/power/mt8183-power.h>
> > + #include <dt-bindings/memory/mt8183-larb-port.h>
> > +
> > + mdp3_rdma0: mdp3-rdma0@...01000 {
> > + compatible = "mediatek,mt8183-mdp3-rdma";
> > + reg = <0x14001000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000
> > 0x1000>;
> > + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
> > + <CMDQ_EVENT_MDP_RDMA0_EOF>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> > + <&mmsys CLK_MM_MDP_RSZ1>;
> > + iommus = <&iommu>;
> > + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
> > + <&gce 21 CMDQ_THR_PRIO_LOWEST>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rsz.yaml
> > new file mode 100644
> > index 000000000000..22c61ed00fdd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rsz.yaml
> > @@ -0,0 +1,77 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8XW2iViE$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8RCccQrB$
> >
> > +
> > +title: MediaTek Resizer
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@...il.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@...iatek.com>
> > +
> > +description: |
> > + One of Media Data Path 3 (MDP3) components used to do frame
> > resizing.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-rsz
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + mediatek,gce-events:
> > + description:
> > + The event id which is mapping to the specific hardware event
> > signal
> > + to gce. The event id is defined in the gce header
> > + include/dt-bindings/gce/<chip>-gce.h of each chips.
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > +
> > + clocks:
> > + minItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - mediatek,gce-events
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > +
> > + mdp3_rsz0: mdp3-rsz0@...03000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
> > + reg = <0x14003000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000
> > 0x1000>;
> > + mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
> > + <CMDQ_EVENT_MDP_RSZ0_EOF>;
> > + clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> > + };
> > +
> > + mdp3_rsz1: mdp3-rsz1@...04000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
> > + reg = <0x14004000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000
> > 0x1000>;
> > + mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
> > + <CMDQ_EVENT_MDP_RSZ1_EOF>;
> > + clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > wrot.yaml
> > new file mode 100644
> > index 000000000000..76c010720d43
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > wrot.yaml
> > @@ -0,0 +1,80 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8Til05HT$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!yGA_w2I4HGhwI-nLMb62fFdTf--h1GdolE2RQhH3DW1AWh0WR0AX4klb8RCccQrB$
> >
> > +
> > +title: MediaTek Write DMA with Rotation
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@...il.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@...iatek.com>
> > +
> > +description: |
> > + One of Media Data Path 3 (MDP3) components used to write DMA
> > with frame rotation.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-wrot
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + mediatek,gce-events:
> > + description:
> > + The event id which is mapping to the specific hardware event
> > signal
> > + to gce. The event id is defined in the gce header
> > + include/dt-bindings/gce/<chip>-gce.h of each chips.
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 1
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - mediatek,gce-events
> > + - power-domains
> > + - clocks
> > + - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > + #include <dt-bindings/power/mt8183-power.h>
> > + #include <dt-bindings/memory/mt8183-larb-port.h>
> > +
> > + mdp3_wrot0: mdp3-wrot0@...05000 {
> > + compatible = "mediatek,mt8183-mdp3-wrot";
> > + reg = <0x14005000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000
> > 0x1000>;
> > + mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
> > + <CMDQ_EVENT_MDP_WROT0_EOF>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_MDP_WROT0>;
> > + iommus = <&iommu>;
> > + };
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