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Message-ID: <537a6b8f-547b-3f12-25a7-90718a1675f3@amd.com>
Date: Mon, 22 Aug 2022 09:11:18 +0530
From: Bharata B Rao <bharata@....com>
To: Andrew Morton <akpm@...ux-foundation.org>
Cc: "Aneesh Kumar K.V" <aneesh.kumar@...ux.ibm.com>,
linux-mm@...ck.org, Wei Xu <weixugc@...gle.com>,
Huang Ying <ying.huang@...el.com>,
Yang Shi <shy828301@...il.com>,
Davidlohr Bueso <dave@...olabs.net>,
Tim C Chen <tim.c.chen@...el.com>,
Michal Hocko <mhocko@...nel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Hesham Almatary <hesham.almatary@...wei.com>,
Dave Hansen <dave.hansen@...el.com>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>,
Alistair Popple <apopple@...dia.com>,
Dan Williams <dan.j.williams@...el.com>,
Johannes Weiner <hannes@...xchg.org>, jvgediya.oss@...il.com
Subject: Re: [PATCH v15 00/10] mm/demotion: Memory tiers and demotion
On 8/20/2022 6:04 AM, Andrew Morton wrote:
> On Fri, 19 Aug 2022 11:57:18 +0530 Bharata B Rao <bharata@....com> wrote:
>
>>> The kernel initialization code makes the decision on which exact tier a memory
>>> node should be assigned to based on the requests from the device drivers as well
>>> as the memory device hardware information provided by the firmware.
>>
>> I gave this patchset a quick try on two setups:
>>
>> 1. With QEMU, when an nvdimm device is bound to dax kmem driver, I can see
>> the memory node with pmem getting into a lower tier than DRAM.
>>
>> 2. In an experimental CXL setup that has DRAM as part of CXL memory, I see that
>> CXL memory node falls into the same tier as the regular DRAM tier. This is
>> expected for now since there is no code (in low level ACPI driver?) yet to
>> map the latency or bandwidth info (when available from firmware) into an
>> abstract distance value, and register a memory type for the same. Guess these
>> bits can be covered as part of future enhancements.
>
> Should I add your Tested-by:?
May be not. I have done only a very minimal testing of specific scenarios
as mentioned above. Thanks for checking.
Regards,
Bharata.
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