linux-kernel - RE: [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding

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Date:   Tue, 23 Aug 2022 02:11:58 +0000
From:   Hongxing Zhu <hongxing.zhu@....com>
To:     Rob Herring <robh@...nel.org>
CC:     "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
        "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "vkoul@...nel.org" <vkoul@...nel.org>,
        "alexander.stein@...tq-group.com" <alexander.stein@...tq-group.com>,
        "marex@...x.de" <marex@...x.de>,
        "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding

> -----Original Message-----
> From: Rob Herring <robh@...nel.org>
> Sent: 2022年8月23日 2:07
> To: Hongxing Zhu <hongxing.zhu@....com>
> Cc: p.zabel@...gutronix.de; l.stach@...gutronix.de; bhelgaas@...gle.com;
> lorenzo.pieralisi@....com; shawnguo@...nel.org; vkoul@...nel.org;
> alexander.stein@...tq-group.com; marex@...x.de;
> linux-phy@...ts.infradead.org; devicetree@...r.kernel.org;
> linux-pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> linux-kernel@...r.kernel.org; kernel@...gutronix.de; dl-linux-imx
> <linux-imx@....com>
> Subject: Re: [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding
> 
> On Thu, Aug 18, 2022 at 03:02:29PM +0800, Richard Zhu wrote:
> > Add i.MX8MP PCIe PHY binding.
> 
> Explain the differences in h/w. The phy is connected to PERST#?
> 
Hi Rob:
Thanks for your review comments.
Yes, it is. PERST# impacts PCIe PHY too.
The default value of this bit is 1b'1 on i.MX8MQ/i.MX8MM platforms. 
But i.MX8MP has one inversed default value 1b'0 of PERST bit.
The PERST bit should be kept 1b'1 after power and clocks are stable.
So add the PHY PERST explicitly for i.MX8MP PCIe PHY.

> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> > ---
> >  .../bindings/phy/fsl,imx8-pcie-phy.yaml          | 16 +++++++++++++---
> >  1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > index b6421eedece3..692783c7fd69 100644
> > --- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > @@ -16,6 +16,7 @@ properties:
> >    compatible:
> >      enum:
> >        - fsl,imx8mm-pcie-phy
> > +      - fsl,imx8mp-pcie-phy
> >
> >    reg:
> >      maxItems: 1
> > @@ -28,11 +29,16 @@ properties:
> >        - const: ref
> >
> >    resets:
> > -    maxItems: 1
> > +    minItems: 1
> > +    maxItems: 2
> >
> >    reset-names:
> > -    items:
> > -      - const: pciephy
> > +    oneOf:
> > +      - items:          # for iMX8MM
> > +          - const: pciephy
> > +      - items:          # for IMX8MP
> > +          - const: pciephy
> > +          - const: perst
> 
> This does the same thing:
> 
> minItems: 1
> items:
>   - const: pciephy
>   - const: perst
> 
Okay, thanks.

Best Regards
Richard Zhu
> 
> >
> >    fsl,refclk-pad-mode:
> >      description: |
> > @@ -60,6 +66,10 @@ properties:
> >      description: A boolean property indicating the CLKREQ# signal is
> >        not supported in the board design (optional)
> >
> > +  power-domains:
> > +    description: PCIe PHY  power domain (optional).
> > +    maxItems: 1
> > +
> >  required:
> >    - "#phy-cells"
> >    - compatible
> > --
> > 2.25.1
> >
> >