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Date: Tue, 23 Aug 2022 10:26:26 +0800 From: Yu Tu <yu.tu@...ogic.com> To: <linux-clk@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-amlogic@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>, Neil Armstrong <narmstrong@...libre.com>, Jerome Brunet <jbrunet@...libre.com>, Kevin Hilman <khilman@...libre.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Martin Blumenstingl <martin.blumenstingl@...glemail.com> CC: Yu Tu <yu.tu@...ogic.com> Subject: [PATCH V4 2/6] arm64: dts: meson: add S4 Soc PLL clock controller in DT Added information about the S4 SOC PLL Clock controller in DT. Signed-off-by: Yu Tu <yu.tu@...ogic.com> --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index ff213618a598..e04c90da348f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -92,6 +92,14 @@ apb4: apb4@...00000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + clkc_pll: clock-controller@...0 { + compatible = "amlogic,s4-pll-clkc"; + reg = <0x0 0x8000 0x0 0x1e8>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + periphs_pinctrl: pinctrl@...0 { compatible = "amlogic,meson-s4-periphs-pinctrl"; #address-cells = <2>; -- 2.33.1
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