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Message-ID: <20220823112615.2e2a96b7@md1za8fc.ad001.siemens.net>
Date: Tue, 23 Aug 2022 11:26:15 +0200
From: Henning Schild <henning.schild@...mens.com>
To: simon.guinot@...uanux.org
Cc: Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>,
Pavel Machek <pavel@....cz>,
Hans de Goede <hdegoede@...hat.com>,
Mark Gross <markgross@...nel.org>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
Lee Jones <lee@...nel.org>, linux-gpio@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-leds@...r.kernel.org,
platform-driver-x86@...r.kernel.org,
Sheng-Yuan Huang <syhuang3@...oton.com>,
Tasanakorn Phaipool <tasanakorn@...il.com>
Subject: Re: [PATCH v3 1/4] gpio-f7188x: Add GPIO support for Nuvoton
NCT6116
Am Fri, 12 Aug 2022 13:22:04 +0200
schrieb simon.guinot@...uanux.org:
> On Fri, Aug 12, 2022 at 12:23:12PM +0200, Henning Schild wrote:
> > Am Fri, 12 Aug 2022 10:43:03 +0200
> > schrieb simon.guinot@...uanux.org:
> >
> > > On Thu, Aug 11, 2022 at 05:39:05PM +0200, Henning Schild wrote:
> > > > Add GPIO support for Nuvoton NCT6116 chip. Nuvoton SuperIO
> > > > chips are very similar to the ones from Fintek. In other
> > > > subsystems they also share drivers and are called a family of
> > > > drivers.
> > > >
> > > > For the GPIO subsystem the only difference is that the direction
> > > > bit is reversed and that there is only one data bit per pin. On
> > > > the SuperIO level the logical device is another one.
> > > >
> > > > Signed-off-by: Henning Schild <henning.schild@...mens.com>
> > > > ---
> > > > drivers/gpio/gpio-f7188x.c | 71
> > > > +++++++++++++++++++++++++++----------- 1 file changed, 51
> > > > insertions(+), 20 deletions(-)
> > > >
> > > > diff --git a/drivers/gpio/gpio-f7188x.c
> > > > b/drivers/gpio/gpio-f7188x.c index 18a3147f5a42..7b05ecc611e9
> > > > 100644 --- a/drivers/gpio/gpio-f7188x.c
> > > > +++ b/drivers/gpio/gpio-f7188x.c
> > > > @@ -1,6 +1,7 @@
> > > > // SPDX-License-Identifier: GPL-2.0-or-later
> > > > /*
> > > > * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882,
> > > > F71889 and F81866
> > > > + * and Nuvoton Super-I/O NCT6116D
> > > > *
> > > > * Copyright (C) 2010-2013 LaCie
> > > > *
> > > > @@ -22,13 +23,12 @@
> > > > #define SIO_LDSEL 0x07 /* Logical device
> > > > select */ #define SIO_DEVID 0x20 /*
> > > > Device ID (2 bytes) */ #define SIO_DEVREV
> > > > 0x22 /* Device revision */ -#define SIO_MANID
> > > > 0x23 /* Fintek ID (2 bytes) */
> > > > -#define SIO_LD_GPIO 0x06 /* GPIO logical
> > > > device */ #define SIO_UNLOCK_KEY 0x87 /*
> > > > Key to enable Super-I/O */ #define SIO_LOCK_KEY
> > > > 0xAA /* Key to disable Super-I/O */
> > > > -#define SIO_FINTEK_ID 0x1934 /*
> > > > Manufacturer ID */ +#define SIO_LD_GPIO_FINTEK
> > > > 0x06 /* GPIO logical device */ +#define
> > > > SIO_LD_GPIO_NUVOTON 0x07 /* GPIO logical device */
> > >
> > > Please indulge me and add a new line here.
> >
> > Mhh ... how about you write exactly how you would like to have that
> > define block. So we do not have taste issues in the next round.
>
> Sure. Considering the manufacturer IDs you have to keep and add, I
> would go with your original approach (i.e. a section per
> manufacturer). But I would add extra new lines and comments and use a
> sligthly different namming for the LD_GPIO definitions.
>
> /*
> * Super-I/O registers
> */
> #define SIO_LDSEL 0x07 /* Logical device select */
> #define SIO_DEVID 0x20 /* Device ID (2 bytes) */
> #define SIO_DEVREV 0x22 /* Device revision */
> #define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
>
> #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
> #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
>
> /*
> * Fintek devices.
> */
> #define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
>
> #define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
> #define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
> #define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
> #define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
> #define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
> #define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
> #define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for
> f81966 */
> #define SIO_F81865_ID 0x0704 /* F81865 chipset ID */
>
> #define SIO_FINTEK_LD_GPIO 0x06 /* GPIO logical device */
>
> /*
> * Nuvoton devices.
> */
> #define SIO_NUVOTON_ID 0xXXXX /* Manufacturer ID */
>
> #define SIO_NCT6116D_ID 0xD283 /* NCT6116D chipset ID */
>
> #define SIO_NUVOTON_LD_GPIO 0x07 /* GPIO logical device */
>
> Please, note it is not only a matter of taste. New lines and comments
> are really helping the reader. Also, note that I am not asking for
> this change, only suggesting it.
This is fine. I will take this. Only slight difference will be in the
revid and manid, those are Fintek specific and do not apply for Nuvoton.
regards,
Henning
> >
> > > > #define SIO_F71869_ID 0x0814 /* F71869
> > > > chipset ID */ #define SIO_F71869A_ID 0x1007
> > > > /* F71869A chipset ID */ #define SIO_F71882_ID
> > > > 0x0541 /* F71882 chipset ID */ @@ -37,7 +37,7 @@
> > > > #define SIO_F81866_ID 0x1010 /* F81866
> > > > chipset ID */ #define SIO_F81804_ID 0x1502 /*
> > > > F81804 chipset ID, same for f81966 */ #define SIO_F81865_ID
> > > > 0x0704 /* F81865 chipset ID */ -
> > > > +#define SIO_NCT6116D_ID 0xD283 /* NCT6116D
> > > > chipset ID */
> > >
> > > ... snip ...
> > >
> > > > @@ -485,12 +516,8 @@ static int __init f7188x_find(int addr,
> > > > struct f7188x_sio *sio) return err;
> > > >
> > > > err = -ENODEV;
> > > > - devid = superio_inw(addr, SIO_MANID);
> > > > - if (devid != SIO_FINTEK_ID) {
> > > > - pr_debug(DRVNAME ": Not a Fintek device at
> > > > 0x%08x\n", addr);
> > > > - goto err;
> > > > - }
> > >
> > > Sorry for missing that at my first review. You can't remove this
> > > block of code. This driver is poking around on the I2C bus, which
> > > is not great. So we want to make sure as much as possible that we
> > > are speaking to the right device.
> >
> > Ok fair enough, we can make that more conservative and match the two
> > manufacturers and also make sure that not one can bring a chip id
> > that the other one uses for another chip.
> > A v4 is coming earliest in 1.5 weeks.
>
> Great. Thanks for your patience.
>
> Simon
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