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Message-ID: <44c86ad9-8158-0a8a-ce31-a995c8d10e0b@gmail.com>
Date: Tue, 23 Aug 2022 12:20:48 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: "Nancy.Lin" <nancy.lin@...iatek.com>,
Rob Herring <robh+dt@...nel.org>,
Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>, wim@...ux-watchdog.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, linux@...ck-us.net,
nfraprado@...labora.com
Cc: David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>,
Nathan Chancellor <nathan@...nel.org>,
Nick Desaulniers <ndesaulniers@...gle.com>,
"jason-jh . lin" <jason-jh.lin@...iatek.com>,
Yongqiang Niu <yongqiang.niu@...iatek.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
dri-devel@...ts.freedesktop.org, llvm@...ts.linux.dev,
singo.chang@...iatek.com,
Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v26 07/10] soc: mediatek: mmsys: add mmsys for support 64
reset bits
On 19/08/2022 08:10, Nancy.Lin wrote:
> Add mmsys for support 64 reset bits. It is a preparation for MT8195
> vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits.
>
> 1. Add the number of reset bits in mmsys private data
> 2. move the whole "reset register code section" behind the
> "get mmsys->data" code section for getting the num_resets in mmsys->data.
>
> Signed-off-by: Nancy.Lin <nancy.lin@...iatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> Reviewed-by: CK Hu <ck.hu@...iatek.com>
> Tested-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>
> ---
> drivers/soc/mediatek/mtk-mmsys.c | 40 +++++++++++++++++++++-----------
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> 2 files changed, 27 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 999be064103b..20ae751ad8a7 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -20,6 +20,8 @@
> #include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> +#define MMSYS_SW_RESET_PER_REG 32
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .clk_driver = "clk-mt2701-mm",
> .routes = mmsys_default_routing_table,
> @@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .routes = mmsys_default_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> + .num_resets = 32,
> };
>
> static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> @@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> + .num_resets = 32,
> };
>
> static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> @@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .routes = mmsys_mt8186_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
> .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> + .num_resets = 32,
> };
>
> static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
> @@ -128,6 +133,7 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .routes = mmsys_mt8192_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> + .num_resets = 32,
You didn't reply to Nicolas regarding the reset numbers. I actually agree with
him that we will need the num_resets declared for all devices. Why do you think
this is not the case?
Regards,
Matthias
> };
>
> static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
> @@ -288,13 +294,19 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
> {
> struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
> unsigned long flags;
> + u32 offset;
> + u32 reg;
> +
> + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> + id = id % MMSYS_SW_RESET_PER_REG;
> + reg = mmsys->data->sw0_rst_offset + offset;
>
> spin_lock_irqsave(&mmsys->lock, flags);
>
> if (assert)
> - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL);
> + mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL);
> else
> - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL);
> + mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL);
>
> spin_unlock_irqrestore(&mmsys->lock, flags);
>
> @@ -351,18 +363,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> return ret;
> }
>
> - spin_lock_init(&mmsys->lock);
> -
> - mmsys->rcdev.owner = THIS_MODULE;
> - mmsys->rcdev.nr_resets = 32;
> - mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> - mmsys->rcdev.of_node = pdev->dev.of_node;
> - ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> - if (ret) {
> - dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
> - return ret;
> - }
> -
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> if (!res) {
> dev_err(dev, "Couldn't get mmsys resource\n");
> @@ -384,6 +384,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> mmsys->data = match_data->drv_data[0];
> }
>
> + spin_lock_init(&mmsys->lock);
> +
> + mmsys->rcdev.owner = THIS_MODULE;
> + mmsys->rcdev.nr_resets = mmsys->data->num_resets;
> + mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> + mmsys->rcdev.of_node = pdev->dev.of_node;
> + ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> + if (ret) {
> + dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
> + return ret;
> + }
> +
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
> if (ret)
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index f01ba206481d..20a271b80b3b 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> const u16 sw0_rst_offset;
> + const u32 num_resets;
> };
>
> struct mtk_mmsys_match_data {
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