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Message-Id: <20220823053846.2684635-11-yung-chuan.liao@linux.intel.com>
Date: Tue, 23 Aug 2022 13:38:45 +0800
From: Bard Liao <yung-chuan.liao@...ux.intel.com>
To: alsa-devel@...a-project.org, vkoul@...nel.org
Cc: vinod.koul@...aro.org, linux-kernel@...r.kernel.org,
pierre-louis.bossart@...ux.intel.com, bard.liao@...el.com
Subject: [PATCH 10/11] soundwire: intel: cleanup AC Timing Control
From: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
Regroup offset and bitfield definitions
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
Reviewed-by: Rander Wang <rander.wang@...el.com>
Signed-off-by: Bard Liao <yung-chuan.liao@...ux.intel.com>
---
include/linux/soundwire/sdw_intel.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h
index a2e1927ac8ac..3a56fd5a6331 100644
--- a/include/linux/soundwire/sdw_intel.h
+++ b/include/linux/soundwire/sdw_intel.h
@@ -76,11 +76,12 @@
#define SDW_SHIM_IOCTL_CIBD BIT(8)
#define SDW_SHIM_IOCTL_DIBD BIT(9)
-#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
-
#define SDW_SHIM_WAKEEN 0x190
#define SDW_SHIM_WAKESTS 0x192
+/* AC Timing control */
+#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
+
#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
#define SDW_SHIM_CTMCTL_DODS BIT(1)
#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
--
2.25.1
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