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Message-Id: <20220823053846.2684635-3-yung-chuan.liao@linux.intel.com>
Date: Tue, 23 Aug 2022 13:38:37 +0800
From: Bard Liao <yung-chuan.liao@...ux.intel.com>
To: alsa-devel@...a-project.org, vkoul@...nel.org
Cc: vinod.koul@...aro.org, linux-kernel@...r.kernel.org,
pierre-louis.bossart@...ux.intel.com, bard.liao@...el.com
Subject: [PATCH 02/11] soundwire: intel: regroup definitions for LCTL
From: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
No functionality change, just regroup offset and bitfield definitions.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
Reviewed-by: Rander Wang <rander.wang@...el.com>
Signed-off-by: Bard Liao <yung-chuan.liao@...ux.intel.com>
---
include/linux/soundwire/sdw_intel.h | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h
index 49a3c265529b..d9f51f43e42c 100644
--- a/include/linux/soundwire/sdw_intel.h
+++ b/include/linux/soundwire/sdw_intel.h
@@ -19,7 +19,14 @@
#define SDW_SHIM_LCAP 0x0
#define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
+/* LCTL */
#define SDW_SHIM_LCTL 0x4
+
+#define SDW_SHIM_LCTL_SPA BIT(0)
+#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
+#define SDW_SHIM_LCTL_CPA BIT(8)
+#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
+
#define SDW_SHIM_IPPTR 0x8
#define SDW_SHIM_SYNC 0xC
@@ -39,11 +46,6 @@
#define SDW_SHIM_WAKEEN 0x190
#define SDW_SHIM_WAKESTS 0x192
-#define SDW_SHIM_LCTL_SPA BIT(0)
-#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
-#define SDW_SHIM_LCTL_CPA BIT(8)
-#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
-
#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
--
2.25.1
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