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Date: Mon, 22 Aug 2022 23:00:52 -0700
From: Colin Foster <colin.foster@...advantage.com>
To: linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-phy@...ts.infradead.org
Cc: UNGLinuxDriver@...rochip.com,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...com>
Subject: [PATCH v1 1/1] dt-bindings: phy: ocelot-serdes: convert to YAML
Convert the phy-ocelot-serdes device tree binding to the new YAML format.
Additionally, add the file to MAINTAINERS since the original file didn't
exist.
Signed-off-by: Colin Foster <colin.foster@...advantage.com>
---
.../bindings/phy/phy-ocelot-serdes.txt | 43 -------------
.../bindings/phy/phy-ocelot-serdes.yaml | 61 +++++++++++++++++++
MAINTAINERS | 1 +
3 files changed, 62 insertions(+), 43 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-ocelot-serdes.yaml
diff --git a/Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt b/Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt
deleted file mode 100644
index 332219860187..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-Microsemi Ocelot SerDes muxing driver
--------------------------------------
-
-On Microsemi Ocelot, there is a handful of registers in HSIO address
-space for setting up the SerDes to switch port muxing.
-
-A SerDes X can be "muxed" to work with switch port Y or Z for example.
-One specific SerDes can also be used as a PCIe interface.
-
-Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
-
-There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
-half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
-10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
-
-Also, SERDES6G number (aka "macro") 0 is the only interface supporting
-QSGMII.
-
-This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
-Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot.
-
-Required properties:
-
-- compatible: should be "mscc,vsc7514-serdes"
-- #phy-cells : from the generic phy bindings, must be 2.
- The first number defines the input port to use for a given
- SerDes macro. The second defines the macro to use. They are
- defined in dt-bindings/phy/phy-ocelot-serdes.h
-
-Example:
-
- serdes: serdes {
- compatible = "mscc,vsc7514-serdes";
- #phy-cells = <2>;
- };
-
- ethernet {
- port1 {
- phy-handle = <&phy_foo>;
- /* Link SERDES1G_5 to port1 */
- phys = <&serdes 1 SERDES1G_5>;
- };
- };
diff --git a/Documentation/devicetree/bindings/phy/phy-ocelot-serdes.yaml b/Documentation/devicetree/bindings/phy/phy-ocelot-serdes.yaml
new file mode 100644
index 000000000000..0666974d886a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-ocelot-serdes.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-ocelot-serdes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microsemi Ocelot SerDes muxing driver
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@...tlin.com>
+ - UNGLinuxDriver@...rochip.com
+
+description: |
+ On Microsemi Ocelot, there is a handful of registers in HSIO address
+ space for setting up the SerDes to switch port muxing.
+
+ A SerDes X can be "muxed" to work with switch port Y or Z for example.
+ One specific SerDes can also be used as a PCIe interface.
+
+ Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
+
+ There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
+ half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
+ 10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
+
+ Also, SERDES6G number (aka "macro") 0 is the only interface supporting
+ QSGMII.
+
+ This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
+ Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot.
+
+properties:
+ compatible:
+ enum:
+ - mscc,vsc7514-serdes
+ "#phy-cells":
+ const: 2
+ description: |
+ from the generic phy bindings, must be 2. The first number
+ defines the input port to use for a given SerDes macro. The
+ second defines the macro to use. They are defined in
+ dt-bindings/phy/phy-ocelot-serdes.h
+
+required:
+ - compatible
+ - "#phy-cells"
+
+examlpes:
+ - |
+ serdes: serdes {
+ compatible = "mscc,vsc7514-serdes";
+ #phy-cells = <2>;
+ };
+
+ ethernet {
+ port1 {
+ phy-handle = <&phy_foo>;
+ /* Link SERDES1G_5 to port1 */
+ phys = <&serdes 1 SERDES1G_5>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 714fd8b45e5a..10dd3c6ad6ad 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13481,6 +13481,7 @@ M: UNGLinuxDriver@...rochip.com
L: linux-mips@...r.kernel.org
S: Supported
F: Documentation/devicetree/bindings/mips/mscc.txt
+F: Documentation/devicetree/bindings/phy/phy-ocelot-serdes.yaml
F: Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
F: arch/mips/boot/dts/mscc/
--
2.25.1
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