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Message-Id: <20220823080231.2466017-9-o.rempel@pengutronix.de>
Date: Tue, 23 Aug 2022 10:02:22 +0200
From: Oleksij Rempel <o.rempel@...gutronix.de>
To: Woojung Huh <woojung.huh@...rochip.com>,
UNGLinuxDriver@...rochip.com, Andrew Lunn <andrew@...n.ch>,
Vivien Didelot <vivien.didelot@...il.com>,
Florian Fainelli <f.fainelli@...il.com>,
Vladimir Oltean <olteanv@...il.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>
Cc: Oleksij Rempel <o.rempel@...gutronix.de>, kernel@...gutronix.de,
linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Subject: [PATCH net-next v3 08/17] net: dsa: microchip: KSZ9893: do not write to not supported Output Clock Control Register
This issue was detected after adding regmap register access validation.
KSZ9893 compatible chips do not have "Output Clock Control Register 0x0103".
So, avoid writing to it.
Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
---
drivers/net/dsa/microchip/ksz9477.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchip/ksz9477.c
index 313a17a989839..54514c9e6e003 100644
--- a/drivers/net/dsa/microchip/ksz9477.c
+++ b/drivers/net/dsa/microchip/ksz9477.c
@@ -193,6 +193,11 @@ int ksz9477_reset_switch(struct ksz_device *dev)
ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
+ /* KSZ9893 compatible chips do not support refclk configuration */
+ if (dev->chip_id == KSZ9893_CHIP_ID ||
+ dev->chip_id == KSZ8563_CHIP_ID)
+ return 0;
+
data8 = SW_ENABLE_REFCLKO;
if (dev->synclko_disable)
data8 = 0;
--
2.30.2
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