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Message-ID: <YwW+UUrn47MCbNIA@kroah.com>
Date: Wed, 24 Aug 2022 07:59:45 +0200
From: Greg KH <gregkh@...uxfoundation.org>
To: Rajat Khandelwal <rajat.khandelwal@...el.corp-partner.google.com>
Cc: heikki.krogerus@...ux.intel.com, rajat.khandelwal@...el.com,
shawn.c.lee@...el.com, linux-usb@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] Enter safe mode only when pins need to be reconfigured
On Wed, Aug 24, 2022 at 07:59:08AM +0200, Greg KH wrote:
> On Tue, Aug 23, 2022 at 10:39:49PM +0530, Rajat Khandelwal wrote:
> > From: Lee Shawn C <shawn.c.lee@...el.com>
> >
> > There is no point to enter safe mode during DP/TBT configuration
> > if the DP/TBT was already configured in mux. This is because safe
> > mode is only applicable when there is a need to reconfigure the
> > pins in order to avoid damage within/to port partner.
> >
> > 1. if HPD interrupt arrives and DP mode was already configured,
> > safe mode is entered again which is not desired.
> > 2. in chrome systems, IOM/mux is already configured before OS
> > comes up. Thus, when driver is probed, it blindly enters safe
> > mode due to PD negotiations but only after gfx driver lowers
> > dp_phy_ownership, will the IOM complete safe mode and send
> > ack to PMC.
> > Since, that never happens, we see IPC timeout.
> >
> > Hence, allow safe mode only when pin reconfiguration is not
> > required, which makes sense.
> >
> > Signed-off-by: Rajat Khandelwal <rajat.khandelwal@...el.com>
> > Signed-off-by: Lee Shawn C <shawn.c.lee@...el.com>
>
> First off, don't use invalid "corp-partner.google.com" email addresses,
> you know that's not going to work and just bounce everywhere and there's
> no proof that this has any relationship to your intel address :(
Also the email verification fails, so it looks like you just spoofed
this message, which also makes it impossible for me to accept.
greg k-h
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