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Message-ID: <CAGETcx846Pomh_DUToncbaOivHMhHrdt-MTVYqkfLUKvM8b=6w@mail.gmail.com>
Date: Thu, 25 Aug 2022 11:38:27 -0700
From: Saravana Kannan <saravanak@...gle.com>
To: Jason Gunthorpe <jgg@...dia.com>
Cc: Greg KH <gregkh@...uxfoundation.org>,
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Subject: Re: [RFC PATCH v2 2/6] bus/cdx: add the cdx bus driver
On Wed, Aug 24, 2022 at 4:31 PM Jason Gunthorpe <jgg@...dia.com> wrote:
>
> On Wed, Aug 24, 2022 at 02:11:48PM +0200, Greg KH wrote:
> > > We can share the RFC in case you are interested in looking at code flow
> > > using the of_dynamic approach.
> >
> > Please no more abuse of the platform device.
>
> Last time this came up there was some disagreement from the ARM folks,
> they were not keen on having xx_drivers added all over the place to
> support the same OF/DT devices just discovered in a different way. It is
> why ACPI is mapped to platform_device even in some cases.
>
> I think if you push them down this path they will get resistance to
> get the needed additional xx_drivers into the needed places.
>
> > If your device can be discovered by scanning a bus, it is not a platform
> > device.
>
> A DT fragment loaded during boot binds a driver using a
> platform_driver, why should a DT fragment loaded post-boot bind using
> an XX_driver and further why should the CDX way of getting the DT
> raise to such importantance that it gets its own cdx_driver ?
>
> In the end the driver does not care about how the DT was loaded.
> None of these things are on a discoverable bus in any sense like PCI
> or otherwise. They are devices described by a DT fragement and they
> take all their parameters from that chunk of DT.
>
> How the DT was loaded into the system is not a useful distinction that
> raises the level of needing an entire new set of xx_driver structs all
> over the tree, IMHO.
Jason, I see your point or rather the point the ARM folks might have
made. But in this case, why not use DT overlays to add these devices?
IIRC there's an in kernel API to add DT overlays. If so, should this
be more of a FPGA driver that reads FPGA stuff and adds DT overlays?
That'd at least make a stronger case for why this isn't a separate
bus.
-Saravana
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