linux-kernel - Re: [PATCH 2/2] riscv: dts: microchip: use an mpfs specific l2 compatible

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Message-ID: <18f0c833-94c6-616c-ce21-384492945240@canonical.com>
Date:   Thu, 25 Aug 2022 21:51:46 +0200
From:   Heinrich Schuchardt <heinrich.schuchardt@...onical.com>
To:     Conor Dooley <conor.dooley@...rochip.com>
Cc:     Sagar Kadam <sagar.kadam@...ive.com>,
        Atish Patra <atishp@...shpatra.org>,
        devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org,
        Daire McNamara <daire.mcnamara@...rochip.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Albert Ou <aou@...s.berkeley.edu>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Rob Herring <robh+dt@...nel.org>,
        Conor Dooley <mail@...chuod.ie>
Subject: Re: [PATCH 2/2] riscv: dts: microchip: use an mpfs specific l2
 compatible



On 8/25/22 20:04, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
> 
> PolarFire SoC does not have the same l2 cache controller as the fu540,
> featuring an extra interrupt. Appease the devicetree checker overlords
> by adding a PolarFire SoC specific compatible to fix the below sort of
> warnings:
> 
> mpfs-polarberry.dtb: cache-controller@...0000: interrupts: [[1], [3], [4], [2]] is too long
> 
> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
> Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@...onical.com>