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Message-ID: <1013c5e6-4027-5294-ff2d-2157073c4779@quicinc.com>
Date: Thu, 25 Aug 2022 10:20:34 +0530
From: Sai Prakash Ranjan <quic_saipraka@...cinc.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
<bjorn.andersson@...aro.org>, <bp@...en8.de>, <mchehab@...nel.org>
CC: <james.morse@....com>, <rric@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <linux-edac@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <quic_tsoni@...cinc.com>
Subject: Re: [PATCH v3 2/5] soc: qcom: llcc: Pass LLCC version based register
offsets to EDAC driver
On 8/25/2022 10:08 AM, Manivannan Sadhasivam wrote:
> The LLCC EDAC register offsets varies between each SoCs. Until now, the
> EDAC driver used the hardcoded register offsets. But this caused crash
> on SM8450 SoC where the register offsets has been changed.
>
> So to avoid this crash and also to make it easy to accommodate changes for
> new SoCs, let's pass the LLCC version specific register offsets to the
> EDAC driver.
>
> Currently, two set of offsets are used. One is starting from LLCC version
> v1.0.0 used by all SoCs other than SM8450. For SM8450, LLCC version
> starting from v2.1.0 is used.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
> drivers/soc/qcom/llcc-qcom.c | 66 ++++++++++++++++++++++++++++++
> include/linux/soc/qcom/llcc-qcom.h | 30 ++++++++++++++
> 2 files changed, 96 insertions(+)
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@...cinc.com>
Thanks,
Sai
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