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Message-ID: <95464d37-6da5-1f63-8f21-93ede5666312@sholland.org>
Date: Thu, 25 Aug 2022 09:37:37 -0500
From: Samuel Holland <samuel@...lland.org>
To: Paul Kocialkowski <paul.kocialkowski@...tlin.com>
Cc: Kishon Vijay Abraham I <kishon@...com>,
Vinod Koul <vkoul@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Maxime Ripard <mripard@...nel.org>,
Jagan Teki <jagan@...rulasolutions.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Maxime Ripard <maxime@...no.tech>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org, linux-sunxi@...ts.linux.dev
Subject: Re: [PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY
variant
On 8/25/22 5:41 AM, Paul Kocialkowski wrote:
> Hi Samuel,
>
> On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
>> A100 features an updated DPHY, which moves PLL control inside the DPHY
>> register space. (Previously PLL-MIPI was controlled from the CCU. This
>> does not affect the "clocks" property because the link between PLL-MIPI
>> and the DPHY was never represented in the devicetree.) It also requires
>> a modified analog power-on sequence. Finally, the new DPHY adds support
>> for operating as an LVDS PHY. D1 uses this same variant.
>
> Do you have some pointers about that? I'd be surprised that this PHY is now
> used for "traditional" LVDS display output, which is usually done with a simpler
> LVDS phy attached to the display controller.
Yes, this is documented in the A133 User Manual. As for the BSP code, see:
https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/lowlevel_v2x/de_dsi.c#L773
https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/lowlevel_v2x/de_lcd_sun50iw10.c#L390
https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/disp_lcd.c#L786
Regards,
Samuel
> However I've seen that some new Allwinner SoCs come with sub-LVDS camera input,
> which typically requires a more complex PHY due to the high number of lanes.
>
> Anyway for now this is:
> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@...tlin.com>
>
> Cheers,
>
> Paul
>
>> Signed-off-by: Samuel Holland <samuel@...lland.org>
>> ---
>>
>> .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> index cf49bd99b3e2..b88c4b52af7d 100644
>> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> @@ -17,9 +17,13 @@ properties:
>> compatible:
>> oneOf:
>> - const: allwinner,sun6i-a31-mipi-dphy
>> + - const: allwinner,sun50i-a100-mipi-dphy
>> - items:
>> - const: allwinner,sun50i-a64-mipi-dphy
>> - const: allwinner,sun6i-a31-mipi-dphy
>> + - items:
>> + - const: allwinner,sun20i-d1-mipi-dphy
>> + - const: allwinner,sun50i-a100-mipi-dphy
>>
>> reg:
>> maxItems: 1
>> --
>> 2.35.1
>>
>
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