linux-kernel - Re: [PATCH v3 4/5] clk: microchip: add PolarFire SoC fabric clock support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <9d41350f-2558-36fc-9863-2d55ecd48b06@microchip.com>
Date:   Fri, 26 Aug 2022 06:45:45 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <Claudiu.Beznea@...rochip.com>, <mturquette@...libre.com>,
        <sboyd@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <palmer@...belt.com>,
        <Daire.McNamara@...rochip.com>, <Hugh.Breslin@...rochip.com>
CC:     <paul.walmsley@...ive.com>, <aou@...s.berkeley.edu>,
        <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH v3 4/5] clk: microchip: add PolarFire SoC fabric clock
 support

On 26/08/2022 07:42, Claudiu Beznea - M18063 wrote:
> On 24.08.2022 12:33, Conor Dooley wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Add a driver to support the PLLs in PolarFire SoC's Clock Conditioning
>> Circuitry, an instance of which is located in each ordinal corner of
>> the FPGA. Only get_rate() is supported as these clocks are intended to
>> be statically configured by the FPGA design. Currently, the DLLs are
>> not supported by this driver. For more information on the hardware, see
>> "PolarFire SoC FPGA Clocking Resources" in the link below.
>>
>> Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
>> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
>> ---

>> +static int mpfs_ccc_probe(struct platform_device *pdev)
>> +{
>> +       struct mpfs_ccc_data *clk_data;
>> +       void __iomem *pll_base[ARRAY_SIZE(mpfs_ccc_pll_clks)];
>> +       unsigned int num_clks;
>> +       int ret;
>> +
>> +       num_clks = ARRAY_SIZE(mpfs_ccc_pll_clks) + ARRAY_SIZE(mpfs_ccc_pll0out_clks)
>> +               + ARRAY_SIZE(mpfs_ccc_pll1out_clks);
>> +
>> +       clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hw_data.hws, num_clks),
>> +                               GFP_KERNEL);
>> +       if (!clk_data)
>> +               return -ENOMEM;
>> +
>> +       pll_base[0] = devm_platform_ioremap_resource(pdev, 0);
>> +       if (IS_ERR(pll_base[0]))
>> +               return PTR_ERR(pll_base[0]);
>> +
>> +       pll_base[1] = devm_platform_ioremap_resource(pdev, 1);
>> +       if (IS_ERR(pll_base[1]))
>> +               return PTR_ERR(pll_base[1]);
>> +
>> +       clk_data->pll_base = pll_base;
>> +       clk_data->dev = &pdev->dev;
>> +
>> +       ret = mpfs_ccc_register_plls(clk_data->dev, mpfs_ccc_pll_clks,
>> +                                    ARRAY_SIZE(mpfs_ccc_pll_clks), clk_data);
>> +       if (ret)
>> +               return ret;
>> +
>> +       ret = devm_of_clk_add_hw_provider(clk_data->dev, of_clk_hw_onecell_get,
>> +                                         &clk_data->hw_data);
>> +       if (ret)
>> +               return ret;
> 
> You can skip this or even directly:
> 	return devm_of_clk_add_hw_provider(...);

That's a left over from copy/pasting our other clock driver's
probe function.. Will simplify in v4 - thanks,
Conor.

> 
>> +
>> +       return ret;
>> +}
>> +