linux-kernel - Re: [RFC PATCH v2 2/6] bus/cdx: add the cdx bus driver

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Message-ID: <YwgO8oCNn/QFM76V@nvidia.com>
Date:   Thu, 25 Aug 2022 21:08:18 -0300
From:   Jason Gunthorpe <jgg@...dia.com>
To:     Robin Murphy <robin.murphy@....com>
Cc:     Saravana Kannan <saravanak@...gle.com>,
        Greg KH <gregkh@...uxfoundation.org>,
        "Gupta, Nipun" <Nipun.Gupta@....com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "rafael@...nel.org" <rafael@...nel.org>,
        "eric.auger@...hat.com" <eric.auger@...hat.com>,
        "alex.williamson@...hat.com" <alex.williamson@...hat.com>,
        "cohuck@...hat.com" <cohuck@...hat.com>,
        "Gupta, Puneet (DCG-ENG)" <puneet.gupta@....com>,
        "song.bao.hua@...ilicon.com" <song.bao.hua@...ilicon.com>,
        "mchehab+huawei@...nel.org" <mchehab+huawei@...nel.org>,
        "maz@...nel.org" <maz@...nel.org>,
        "f.fainelli@...il.com" <f.fainelli@...il.com>,
        "jeffrey.l.hugo@...il.com" <jeffrey.l.hugo@...il.com>,
        "Michael.Srba@...nam.cz" <Michael.Srba@...nam.cz>,
        "mani@...nel.org" <mani@...nel.org>,
        "yishaih@...dia.com" <yishaih@...dia.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "okaya@...nel.org" <okaya@...nel.org>,
        "Anand, Harpreet" <harpreet.anand@....com>,
        "Agarwal, Nikhil" <nikhil.agarwal@....com>,
        "Simek, Michal" <michal.simek@....com>,
        "git (AMD-Xilinx)" <git@....com>
Subject: Re: [RFC PATCH v2 2/6] bus/cdx: add the cdx bus driver

On Thu, Aug 25, 2022 at 08:57:49PM +0100, Robin Murphy wrote:

> To my mind, it would definitely help to understand if this is a *real*
> discoverable bus in hardware, i.e. does one have to configure one's device
> with some sort of CDX wrapper at FPGA synthesis time, that then physically
> communicates with some sort of CDX controller to identify itself once
> loaded; or is it "discoverable" in the sense that there's some firmware on
> an MCU controlling what gets loaded into the FPGA, and software can query
> that and get back whatever precompiled DTB fragment came bundled with the
> bitstream, i.e. it's really more like fpga-mgr in a fancy hat?

So much of the IP that you might want to put in a FPGA needs DT, I
don't thing a simplistic AMBA like discoverable thing would be that
interesting.

Think about things like FPGA GPIOs being configured as SPI/I2C, then
describing the board config of SPI/I2C busses, setting up PCI bridges,
flash storage controllers and all sorts of other typically embedded
stuff that really relies on DT these days.

It would be nice if Xilinx could explain more about what environment
this is targetting. Is it Zynq-like stuff?

Jason