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Date:   Sat, 27 Aug 2022 12:22:21 +0300
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Conor Dooley <conor.dooley@...rochip.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Daire McNamara <daire.mcnamara@...rochip.com>,
        Shravan Chippa <shravan.chippa@...rochip.com>
Cc:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Cyril Jean <Cyril.Jean@...rochip.com>,
        Lewis Hanly <lewis.hanly@...rochip.com>,
        Vattipalli Praveen <praveen.kumar@...rochip.com>,
        Wolfgang Grandegger <wg@...es-embedded.de>,
        devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/9] dt-bindings: riscv: microchip: document the aries
 m100pfsevp

On 26/08/2022 17:28, Conor Dooley wrote:
> Add compatibles for both configurations of the Aries Embedded
> M100PFSEVP SOM + EVK platform.
> 
> Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
>  Documentation/devicetree/bindings/riscv/microchip.yaml | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
> index 7cfc96c21ab0..04ebd48caaa7 100644
> --- a/Documentation/devicetree/bindings/riscv/microchip.yaml
> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
> @@ -26,9 +26,13 @@ properties:
>            - const: microchip,mpfs
>  
>        - items:
> -          - const: sundance,polarberry
> +          - enum:

Make it an enum already in your first patch, so you won't need to change
same lines.


Best regards,
Krzysztof

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