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Message-ID: <CADnq5_O6b5bhpppqjOrnXhyfk+jXeMcYiQCDLXDz_HcCujQ4Ag@mail.gmail.com>
Date: Mon, 29 Aug 2022 15:45:55 -0400
From: Alex Deucher <alexdeucher@...il.com>
To: cgel.zte@...il.com
Cc: harry.wentland@....com, sunpeng.li@....com,
Rodrigo.Siqueira@....com, alexander.deucher@....com,
christian.koenig@....com, Xinhui.Pan@....com, airlied@...ux.ie,
daniel@...ll.ch, Anthony.Koo@....com, alex.hung@....com,
Roman.Li@....com, Yi-Ling.Chen2@....com, hanghong.ma@....com,
mwen@...lia.com, dingchen.zhang@....com, dale.zhao@....com,
Zeal Robot <zealci@....com.cn>, linux-kernel@...r.kernel.org,
amd-gfx@...ts.freedesktop.org, Jerry.Zuo@....com,
dri-devel@...ts.freedesktop.org, isabbasso@...eup.net,
Jinpeng Cui <cui.jinpeng2@....com.cn>,
agustin.gutierrez@....com, Sungjoon.Kim@....com
Subject: Re: [PATCH linux-next] drm/amd/display: remove redundant
vertical_line_start variable
Applied. Thanks!
Alex
On Mon, Aug 29, 2022 at 8:13 AM <cgel.zte@...il.com> wrote:
>
> From: Jinpeng Cui <cui.jinpeng2@....com.cn>
>
> Return value from expression directly instead of
> taking this in another redundant variable.
>
> Reported-by: Zeal Robot <zealci@....com.cn>
> Signed-off-by: Jinpeng Cui <cui.jinpeng2@....com.cn>
> ---
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index 37246e965457..8f4f1ea447a7 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -3741,7 +3741,6 @@ int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
> int vesa_sync_start;
> int asic_blank_end;
> int interlace_factor;
> - int vertical_line_start;
>
> patched_crtc_timing = *dc_crtc_timing;
> apply_front_porch_workaround(&patched_crtc_timing);
> @@ -3757,10 +3756,8 @@ int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
> patched_crtc_timing.v_border_top)
> * interlace_factor;
>
> - vertical_line_start = asic_blank_end -
> + return asic_blank_end -
> pipe_ctx->pipe_dlg_param.vstartup_start + 1;
> -
> - return vertical_line_start;
> }
>
> void dcn10_calc_vupdate_position(
> --
> 2.25.1
>
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