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Message-ID: <1661754153-14813-2-git-send-email-quic_c_skakit@quicinc.com>
Date: Mon, 29 Aug 2022 11:52:29 +0530
From: Satya Priya <quic_c_skakit@...cinc.com>
To: Rob Herring <robh@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>
CC: Douglas Anderson <dianders@...omium.org>,
Stephen Boyd <swboyd@...omium.org>,
Andy Gross <agross@...nel.org>, <devicetree@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_tdas@...cinc.com>, <quic_c_skakit@...cinc.com>,
<linux-clk@...r.kernel.org>
Subject: [PATCH V8 1/5] dt-bindings: clock: Add "qcom,adsp-pil-mode" property
When this property is set, the remoteproc is used to boot the
LPASS and therefore lpass_q6ss_ahbm_clk and lpass_q6ss_ahbs_clk
clocks would be used to bring LPASS out of reset and the rest of
the lpass clocks would be controlled directly by the remoteproc.
This is a cleanup done to handle overlap of regmap of
lpasscc and lpass_aon blocks.
Signed-off-by: Satya Priya <quic_c_skakit@...cinc.com>
Signed-off-by: Taniya Das <quic_tdas@...cinc.com>
Reviewed-by: Rob Herring <robh@...nel.org>
Reviewed-by: Stephen Boyd <sboyd@...nel.org>
---
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 6 ++----
.../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml | 7 +++++++
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 47028d7..633887d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -36,13 +36,11 @@ properties:
items:
- description: LPASS qdsp6ss register
- description: LPASS top-cc register
- - description: LPASS cc register
reg-names:
items:
- const: qdsp6ss
- const: top_cc
- - const: cc
required:
- compatible
@@ -59,8 +57,8 @@ examples:
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
clock-controller@...0000 {
compatible = "qcom,sc7280-lpasscc";
- reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>;
- reg-names = "qdsp6ss", "top_cc", "cc";
+ reg = <0x03000000 0x40>, <0x03c04000 0x4>;
+ reg-names = "qdsp6ss", "top_cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
index bad9135..5ccfb24 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
@@ -41,6 +41,12 @@ properties:
reg:
maxItems: 1
+ qcom,adsp-pil-mode:
+ description:
+ Indicates if the LPASS would be brought out of reset using
+ peripheral loader.
+ type: boolean
+
required:
- compatible
- reg
@@ -165,6 +171,7 @@ examples:
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&lpasscore LPASS_CORE_CC_CORE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
+ qcom,adsp-pil-mode;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
--
2.7.4
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