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Message-ID: <d009d829-54d5-7b96-cfbb-3f75515a29fe@microchip.com>
Date: Mon, 29 Aug 2022 06:45:06 +0000
From: <Conor.Dooley@...rochip.com>
To: <zong.li@...ive.com>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <palmer@...belt.com>,
<paul.walmsley@...ive.com>, <aou@...s.berkeley.edu>,
<greentime.hu@...ive.com>, <devicetree@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to
composible cache
Hey Zong,
Couple quick comments for you:
On 29/08/2022 07:22, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Since composible cache may be L3 cache if private L2 cache exists, it
s/composible/composable
> should use its original name composible cache to prevent confusion.
s/composible/composable
>
> Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
> Signed-off-by: Zong Li <zong.li@...ive.com>
> ---
> .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
> rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> similarity index 92%
> rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> index 69cdab18d629..1a64a5384e36 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
Binding filenames are supposed to match the first compatible. Since
it was not named that way in the first place, I suppose naming after
the generic compatible makes the most sense. The correct filename
would then be "sifive,ccache0.yaml"
> @@ -12,8 +12,8 @@ maintainers:
> - Paul Walmsley <paul.walmsley@...ive.com>
>
> description:
> - The SiFive Level 2 Cache Controller is used to provide access to fast copies
> - of memory for masters in a Core Complex. The Level 2 Cache Controller also
> + The SiFive Composable Cache Controller is used to provide access to fast copies
> + of memory for masters in a Core Complex. The Composable Cache Controller also
> acts as directory-based coherency manager.
> All the properties in ePAPR/DeviceTree specification applies for this platform.
>
> @@ -27,6 +27,7 @@ select:
> enum:
> - sifive,fu540-c000-ccache
> - sifive,fu740-c000-ccache
> + - sifive,ccache0
Despite what the commit message says, this is more than a rename.
Thanks,
Conor.
>
> required:
> - compatible
> @@ -37,6 +38,7 @@ properties:
> - enum:
> - sifive,fu540-c000-ccache
> - sifive,fu740-c000-ccache
> + - sifive,ccache0
> - const: cache
>
> cache-block-size:
> --
> 2.17.1
>
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