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Message-Id: <20220829105815.715256099@linuxfoundation.org>
Date: Mon, 29 Aug 2022 13:00:07 +0200
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
stable@...r.kernel.org, Conor Dooley <conor.dooley@...rochip.com>
Subject: [PATCH 5.19 157/158] riscv: dts: microchip: mpfs: remove pci axi address translation property
From: Conor Dooley <conor.dooley@...rochip.com>
commit e4009c5fa77b4356aa37ce002e9f9952dfd7a615 upstream.
An AXI master address translation table property was inadvertently
added to the device tree & this was not caught by dtbs_check at the
time. Remove the property - it should not be in mpfs.dtsi anyway as
it would be more suitable in -fabric.dtsi nor does it actually apply
to the version of the reference design we are using for upstream.
Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 -
1 file changed, 1 deletion(-)
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -446,7 +446,6 @@
ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
msi-parent = <&pcie>;
msi-controller;
- microchip,axi-m-atr0 = <0x10 0x0>;
status = "disabled";
pcie_intc: interrupt-controller {
#address-cells = <0>;
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