linux-kernel - Re: [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible

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Message-ID: <20220830215900.GA2162133-robh@kernel.org>
Date:   Tue, 30 Aug 2022 16:59:00 -0500
From:   Rob Herring <robh@...nel.org>
To:     Conor Dooley <mail@...chuod.ie>
Cc:     Daire McNamara <daire.mcnamara@...rochip.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        linux-riscv@...ts.infradead.org,
        Sagar Kadam <sagar.kadam@...ive.com>,
        Atish Patra <atishp@...shpatra.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Rob Herring <robh+dt@...nel.org>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>
Subject: Re: [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC
 compatible

On Thu, 25 Aug 2022 19:04:17 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
> 
> The l2 cache on PolarFire SoC is cross between that of the fu540 and
> the fu740. It has the extra interrupt from the fu740 but the lower
> number of cache-sets. Add a specific compatible to avoid the likes
> of:
> 
> mpfs-polarberry.dtb: cache-controller@...0000: interrupts: [[1], [3], [4], [2]] is too long
> 
> Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
>  .../bindings/riscv/sifive-l2-cache.yaml       | 79 ++++++++++++-------
>  1 file changed, 49 insertions(+), 30 deletions(-)
> 

Reviewed-by: Rob Herring <robh@...nel.org>