linux-kernel - RE: [PATCH] clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round

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Message-ID: <BY5PR12MB4902F502F67AEC1B575A867281799@BY5PR12MB4902.namprd12.prod.outlook.com>
Date:   Tue, 30 Aug 2022 06:18:55 +0000
From:   "Datta, Shubhrajyoti" <shubhrajyoti.datta@....com>
To:     "quanyang.wang@...driver.com" <quanyang.wang@...driver.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Michal Simek <michal.simek@...inx.com>
CC:     Michael Tretter <m.tretter@...gutronix.de>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] clk: zynqmp: pll: rectify rate rounding in
 zynqmp_pll_round_rate

[AMD Official Use Only - General]

Hi ,
Thanks for the patch.

> -----Original Message-----
> From: quanyang.wang@...driver.com <quanyang.wang@...driver.com>
> Sent: Friday, August 26, 2022 7:51 PM
> To: Michael Turquette <mturquette@...libre.com>; Stephen Boyd
> <sboyd@...nel.org>; Michal Simek <michal.simek@...inx.com>
> Cc: Michael Tretter <m.tretter@...gutronix.de>; Quanyang Wang
> <quanyang.wang@...driver.com>; linux-clk@...r.kernel.org; linux-arm-
> kernel@...ts.infradead.org; linux-kernel@...r.kernel.org
> Subject: [PATCH] clk: zynqmp: pll: rectify rate rounding in
> zynqmp_pll_round_rate
> 
> CAUTION: This message has originated from an External Source. Please use
> proper judgment and caution when opening attachments, clicking links, or
> responding to this email.
> 
> 
> From: Quanyang Wang <quanyang.wang@...driver.com>
> 
> The function zynqmp_pll_round_rate is used to find a most appropriate PLL
> frequency which the hardware can generate according to the desired
> frequency. For example, if the desired frequency is 297MHz, considering the
> limited range from PS_PLL_VCO_MIN (1.5GHz) to PS_PLL_VCO_MAX (3.0GHz)
> of PLL, zynqmp_pll_round_rate should return 1.872GHz (297MHz * 5).
> 
> There are two problems with the current code of zynqmp_pll_round_rate:
> 
> 1) When the rate is below PS_PLL_VCO_MIN, it can't find a correct rate when
> the parameter "rate" is an integer multiple of *prate, in other words, if "f" is
> zero, zynqmp_pll_round_rate won't return a valid frequency which is from
> PS_PLL_VCO_MIN to PS_PLL_VCO_MAX. For example, *prate is 33MHz and
> the rate is 660MHz, zynqmp_pll_round_rate will not boost up rate and just
> return 660MHz, and this will cause clk_calc_new_rates failure since
> zynqmp_pll_round_rate returns an invalid rate out of its boundaries.
> 
> 2) Even if the rate is higher than PS_PLL_VCO_MIN, there is still a risk that
> zynqmp_pll_round_rate returns an invalid rate because the function
> DIV_ROUND_CLOSEST makes some loss in the fractional part. If the parent
> clock *prate is 33333333Hz and we want to set the PLL rate to 1.5GHz, this
> function will return 1499999985Hz by using the formula below:
>     value = *prate * DIV_ROUND_CLOSEST(rate, *prate)).
> This value is also invalid since it's slightly smaller than PS_PLL_VCO_MIN.
> because DIV_ROUND_CLOSEST makes some loss in the fractional part.
> 
> Signed-off-by: Quanyang Wang <quanyang.wang@...driver.com>
Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@....com>