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Message-ID: <Yw3AHmMG9G1g9ruZ@matsya>
Date: Tue, 30 Aug 2022 13:15:34 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Lucas Stach <l.stach@...gutronix.de>
Cc: Richard Zhu <hongxing.zhu@....com>, p.zabel@...gutronix.de,
bhelgaas@...gle.com, lorenzo.pieralisi@....com, robh@...nel.org,
shawnguo@...nel.org, alexander.stein@...tq-group.com,
marex@...x.de, richard.leitner@...ux.dev,
linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, kernel@...gutronix.de,
linux-imx@....com
Subject: Re: [PATCH 2/2] fixup! phy: freescale: imx8m-pcie: Add iMX8MP PCIe
PHY support
On 29-08-22, 17:16, Lucas Stach wrote:
> ---
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 31 +++-------------------
> 1 file changed, 3 insertions(+), 28 deletions(-)
Pls squash and resend the patch properly!
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> index 3463b4299f2f..f714f419b91f 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> @@ -13,6 +13,7 @@
> #include <linux/module.h>
> #include <linux/of_address.h>
> #include <linux/of_device.h>
> +#include <linux/of_device.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> @@ -47,10 +48,6 @@
> #define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
> #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
>
> -#define IMX8MP_GPR_REG0 0x0
> -#define IMX8MP_GPR_PHY_APB_RST BIT(4)
> -#define IMX8MP_GPR_PHY_INIT_RST BIT(5)
> -
> enum imx8_pcie_phy_type {
> IMX8MM,
> IMX8MP,
> @@ -58,10 +55,8 @@ enum imx8_pcie_phy_type {
>
> struct imx8_pcie_phy {
> void __iomem *base;
> - struct device *dev;
> struct clk *clk;
> struct phy *phy;
> - struct regmap *hsio_blk_ctrl;
> struct regmap *iomuxc_gpr;
> struct reset_control *reset;
> struct reset_control *perst;
> @@ -93,13 +88,6 @@ static int imx8_pcie_phy_init(struct phy *phy)
> break;
> case IMX8MP:
> reset_control_assert(imx8_phy->perst);
> -
> - /* release pcie_phy_apb_reset and pcie_phy_init_resetn */
> - regmap_update_bits(imx8_phy->hsio_blk_ctrl, IMX8MP_GPR_REG0,
> - IMX8MP_GPR_PHY_APB_RST |
> - IMX8MP_GPR_PHY_INIT_RST,
> - IMX8MP_GPR_PHY_APB_RST |
> - IMX8MP_GPR_PHY_INIT_RST);
> break;
> }
>
> @@ -204,21 +192,16 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> {
> struct phy_provider *phy_provider;
> struct device *dev = &pdev->dev;
> - const struct of_device_id *of_id;
> struct device_node *np = dev->of_node;
> struct imx8_pcie_phy *imx8_phy;
> struct resource *res;
>
> - of_id = of_match_device(imx8_pcie_phy_of_match, dev);
> - if (!of_id)
> - return -EINVAL;
> -
> imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL);
> if (!imx8_phy)
> return -ENOMEM;
>
> - imx8_phy->dev = dev;
> - imx8_phy->variant = (enum imx8_pcie_phy_type)of_id->data;
> + imx8_phy->variant =
> + (enum imx8_pcie_phy_type)of_device_get_match_data(dev);
>
> /* get PHY refclk pad mode */
> of_property_read_u32(np, "fsl,refclk-pad-mode",
> @@ -257,14 +240,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> return PTR_ERR(imx8_phy->reset);
> }
> if (imx8_phy->variant == IMX8MP) {
> - /* Grab HSIO MIX config register range */
> - imx8_phy->hsio_blk_ctrl =
> - syscon_regmap_lookup_by_compatible("fsl,imx8mp-hsio-blk-ctrl");
> - if (IS_ERR(imx8_phy->hsio_blk_ctrl)) {
> - dev_err(dev, "Unable to find HSIO MIX registers\n");
> - return PTR_ERR(imx8_phy->hsio_blk_ctrl);
> - }
> -
> imx8_phy->perst =
> devm_reset_control_get_exclusive(dev, "perst");
> if (IS_ERR(imx8_phy->perst)) {
> --
> 2.30.2
--
~Vinod
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