linux-kernel - [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

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Message-Id: <20220830083606.1681385-1-ben.dooks@sifive.com>
Date:   Tue, 30 Aug 2022 09:36:06 +0100
From:   Ben Dooks <ben.dooks@...ive.com>
To:     palmer@...belt.com, paul.walmsley@...ive.com,
        aou@...s.berkeley.edu, greentime.hu@...ive.com,
        conor.dooley@...rochip.com, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org
Cc:     Ben Dooks <ben.dooks@...ive.com>
Subject: [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

With newer cores such as the p550, the SiFive composable cache can be
a level 3 cache. Update the cache level to be one of 2 or 3.

Signed-off-by: Ben Dooks <ben.dooks@...ive.com>
---
 Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
index 1a64a5384e36..6190deb65455 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
@@ -45,7 +45,7 @@ properties:
     const: 64
 
   cache-level:
-    const: 2
+    enum: [2, 3]
 
   cache-sets:
     enum: [1024, 2048]
-- 
2.35.1