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Message-ID: <bbdb3953-eaaf-8efa-a55a-9ca083320af7@microchip.com>
Date: Tue, 30 Aug 2022 12:06:22 +0000
From: <Conor.Dooley@...rochip.com>
To: <ben.dooks@...ethink.co.uk>
CC: <paul.walmsley@...ive.com>, <krzysztof.kozlowski+dt@...aro.org>,
<palmer@...belt.com>, <Shravan.Chippa@...rochip.com>,
<aou@...s.berkeley.edu>, <Cyril.Jean@...rochip.com>,
<Lewis.Hanly@...rochip.com>, <Praveen.Kumar@...rochip.com>,
<wg@...es-embedded.de>, <Hugh.Breslin@...rochip.com>,
<robh+dt@...nel.org>, <devicetree@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<Daire.McNamara@...rochip.com>
Subject: Re: [PATCH v2 6/9] riscv: dts: microchip: icicle: update pci address
properties
On 30/08/2022 11:44, Ben Dooks wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 30/08/2022 11:18, Conor Dooley wrote:
>> For the v2022.09 reference design the PCI root port's data region has
>> been moved to FIC1 from FIC0. This is a shorter path, allowing for
>> higher clock rates and improved through-put. As a result, the address at
>> which the PCIe's data region appears to the core complex has changed.
>> The config region's address is unchanged.
>
> Did this also fix the 32bit address apperture issue which plagued
> getting pcie graphics cards sorted.
Eh, not this specific part of what is changing in v2022.09 - this will
just allow us to close timing using higher clock rates. But another
change that is landing in v2022.09 will (see patch 4/9). Performance is
not going to be great, but 32 bit devices will work again... We've got
some more stuff in the works that should help on the performance front,
so hopefully that makes life easier for pcie graphics cards.
soonTM on that one though ;)
Thanks,
Conor.
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