linux-kernel - Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

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Message-ID: <b810d354-18f3-9ae0-6310-57d9e36f4f9b@microchip.com>
Date:   Tue, 30 Aug 2022 12:56:34 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <ben.dooks@...ive.com>, <palmer@...belt.com>,
        <paul.walmsley@...ive.com>, <aou@...s.berkeley.edu>,
        <greentime.hu@...ive.com>, <linux-kernel@...r.kernel.org>,
        <linux-riscv@...ts.infradead.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <devicetree@...r.kernel.org>
Subject: Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3
 cache

On 30/08/2022 13:51, Ben Dooks wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> With newer cores such as the p550, the SiFive composable cache can be
> a level 3 cache. Update the cache level to be one of 2 or 3.
> 
> Signed-off-by: Ben Dooks <ben.dooks@...ive.com>
> ---
>   Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> index 1a64a5384e36..6190deb65455 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> @@ -45,7 +45,7 @@ properties:
>       const: 64
> 
>     cache-level:
> -    const: 2
> +    enum: [2, 3]

Do we want to enforce the cache level like we currently do for
interrupts and cache-sets?