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Date: Wed, 31 Aug 2022 19:24:57 +0200
From: Andrew Jones <ajones@...tanamicro.com>
To: linux-riscv@...ts.infradead.org, kvm-riscv@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org, paul.walmsley@...ive.com,
palmer@...belt.com, aou@...s.berkeley.edu, anup@...infault.org,
mchitale@...tanamicro.com, heiko@...ech.de
Subject: [PATCH v2 1/4] riscv: Add X register names to gpr-nums
When encoding instructions it's sometimes necessary to set a
register field to a precise number. This is easiest to do using
the x<num> naming.
Signed-off-by: Andrew Jones <ajones@...tanamicro.com>
Reviewed-by: Anup Patel <anup@...infault.org>
---
arch/riscv/include/asm/gpr-num.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/gpr-num.h b/arch/riscv/include/asm/gpr-num.h
index dfee2829fc7c..efeb5edf8a3a 100644
--- a/arch/riscv/include/asm/gpr-num.h
+++ b/arch/riscv/include/asm/gpr-num.h
@@ -3,6 +3,11 @@
#define __ASM_GPR_NUM_H
#ifdef __ASSEMBLY__
+
+ .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+ .equ .L__gpr_num_x\num, \num
+ .endr
+
.equ .L__gpr_num_zero, 0
.equ .L__gpr_num_ra, 1
.equ .L__gpr_num_sp, 2
@@ -39,6 +44,9 @@
#else /* __ASSEMBLY__ */
#define __DEFINE_ASM_GPR_NUMS \
+" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31\n" \
+" .equ .L__gpr_num_x\\num, \\num\n" \
+" .endr\n" \
" .equ .L__gpr_num_zero, 0\n" \
" .equ .L__gpr_num_ra, 1\n" \
" .equ .L__gpr_num_sp, 2\n" \
--
2.37.2
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