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Message-ID: <37ed6be6-bfa5-e87c-9c74-e5bdacda1600@intel.com>
Date:   Wed, 31 Aug 2022 11:40:24 +0800
From:   Xiaoyao Li <xiaoyao.li@...el.com>
To:     Isaku Yamahata <isaku.yamahata@...il.com>,
        Sean Christopherson <seanjc@...gle.com>
Cc:     Binbin Wu <binbin.wu@...ux.intel.com>, isaku.yamahata@...el.com,
        kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
        Paolo Bonzini <pbonzini@...hat.com>, erdemaktas@...gle.com,
        Sagi Shahar <sagis@...gle.com>
Subject: Re: [PATCH v8 018/103] KVM: TDX: Stub in tdx.h with structs,
 accessors, and VMCS helpers

On 8/26/2022 12:48 PM, Isaku Yamahata wrote:
> On Tue, Aug 23, 2022 at 03:40:40PM +0000,
> Sean Christopherson <seanjc@...gle.com> wrote:
> 
>> On Tue, Aug 23, 2022, Binbin Wu wrote:
>>>
>>> On 2022/8/8 6:01, isaku.yamahata@...el.com wrote:
>>>> +static __always_inline void tdvps_vmcs_check(u32 field, u8 bits)
>>>> +{
>>>> +	BUILD_BUG_ON_MSG(__builtin_constant_p(field) && (field) & 0x1,
>>>> +			 "Read/Write to TD VMCS *_HIGH fields not supported");
>>>> +
>>>> +	BUILD_BUG_ON(bits != 16 && bits != 32 && bits != 64);
>>>> +
>>>> +	BUILD_BUG_ON_MSG(bits != 64 && __builtin_constant_p(field) &&
>>>> +			 (((field) & 0x6000) == 0x2000 ||
>>>> +			  ((field) & 0x6000) == 0x6000),
>>>> +			 "Invalid TD VMCS access for 64-bit field");
>>>
>>> if bits is 64 here, "bits != 64" is false, how could this check for "Invalid
>>> TD VMCS access for 64-bit field"?
>>
>> Bits 14:13 of the encoding, which is extracted by "(field) & 0x6000", encodes the
>> width of the VMCS field.  Bit 0 of the encoding, "(field) & 0x1" above, is a modifier
>> that is only relevant when operating in 32-bit mode, and is disallowed because TDX is
>> 64-bit only.
>>
>> This yields four possibilities for TDX:
>>
>>    (field) & 0x6000) == 0x0000 : 16-bit field
>>    (field) & 0x6000) == 0x2000 : 64-bit field
>>    (field) & 0x6000) == 0x4000 : 32-bit field
>>    (field) & 0x6000) == 0x6000 : 64-bit field (technically "natural width", but
>>                                                effectively 64-bit because TDX is
>> 					      64-bit only)
>>
>> The assertion is that if the encoding indicates a 64-bit field (0x2000 or 0x6000),
>> then the number of bits KVM is accessing must be '64'.  The below assertions do
>> the same thing for 32-bit and 16-bit fields.
> 
> Thanks for explanation. I've updated it as follows to use symbolic value.
> 
> #define VMCS_ENC_ACCESS_TYPE_MASK	0x1UL
> #define VMCS_ENC_ACCESS_TYPE_FULL	0x0UL
> #define VMCS_ENC_ACCESS_TYPE_HIGH	0x1UL
> #define VMCS_ENC_ACCESS_TYPE(field)	((field) & VMCS_ENC_ACCESS_TYPE_MASK)
> 
> 	/* TDX is 64bit only.  HIGH field isn't supported. */
> 	BUILD_BUG_ON_MSG(__builtin_constant_p(field) &&
> 			 VMCS_ENC_ACCESS_TYPE(field) == VMCS_ENC_ACCESS_TYPE_HIGH,
> 			 "Read/Write to TD VMCS *_HIGH fields not supported");
> 
> 	BUILD_BUG_ON(bits != 16 && bits != 32 && bits != 64);
> 
> #define VMCS_ENC_WIDTH_MASK	GENMASK_UL(14, 13)
> #define VMCS_ENC_WIDTH_16BIT	(0UL << 13)
> #define VMCS_ENC_WIDTH_64BIT	(1UL << 13)
> #define VMCS_ENC_WIDTH_32BIT	(2UL << 13)
> #define VMCS_ENC_WIDTH_NATURAL	(3UL << 13)
> #define VMCS_ENC_WIDTH(field)	((field) & VMCS_ENC_WIDTH_MASK)
> 
> 	/* TDX is 64bit only.  i.e. natural width = 64bit. */
> 	BUILD_BUG_ON_MSG(bits != 64 && __builtin_constant_p(field) &&
> 			 (VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_64BIT ||
> 			  VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_NATURAL),
> 			 "Invalid TD VMCS access for 64-bit field");
> 	BUILD_BUG_ON_MSG(bits != 32 && __builtin_constant_p(field) &&
> 			 VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_32BIT,
> 			 "Invalid TD VMCS access for 32-bit field");
> 	BUILD_BUG_ON_MSG(bits != 16 && __builtin_constant_p(field) &&
> 			 VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_16BIT,
> 			 "Invalid TD VMCS access for 16-bit field");

Actually, the original code is written by me that is copied from 
vmcs_check{16/32/64/l} in arch/x86/kvm/vmx/vmx_ops.h

If you are going to do above change, you'd better cook a patch to change 
it for vmx_ops.h at first and see opinion from community.

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