linux-kernel - Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

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Message-ID: <0deb3350-5a4a-8850-7dc1-e7e5b7e9bfdd@microchip.com>
Date:   Wed, 31 Aug 2022 06:25:48 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <zongbox@...il.com>
CC:     <ben.dooks@...ethink.co.uk>, <ben.dooks@...ive.com>,
        <palmer@...belt.com>, <paul.walmsley@...ive.com>,
        <aou@...s.berkeley.edu>, <greentime.hu@...ive.com>,
        <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <devicetree@...r.kernel.org>
Subject: Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3
 cache

On 31/08/2022 06:17, Zong Li wrote:
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> <Conor.Dooley@...rochip.com> 於 2022年8月31日 週三 凌晨1:09寫道：
>> That would keep the enforcement for existing caches and allow you
>> the freedome to do w/e you want for the ccache0 compatible.
> 
> Thanks you all for bring me here,  we actually have some core series
> with 4096 cache set in ccache, should we need to extend the cache set
> as follow? or we only need to focus on the DTS which is already in
> mainline.
> 
> cache-sets:
> -    enum: [1024, 2048]
> +   enum: [1024, 2048, 4096]

Until a user shows up, I think we are better off not adding 4096.

>>> Do we need someone to take charge of this series?
>>>
>>
>> Can I volunteer Zong? (since all but two of the patches are theirs)
>>
> 
> It is ok to me, but I'm still refining the patchset for V2, and I'm
> not sure if we will need the V3. Do you prefer to take V2 patch set
> first and replace the dt-binding patch?

If you could incorporate it for v2 it would make reviewing easier
I think.

Thanks,
Conor.