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Date:   Wed, 31 Aug 2022 15:19:38 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Lewis.Hanly@...rochip.com
Cc:     linux-riscv@...ts.infradead.org, Conor.Dooley@...rochip.com,
        brgl@...ev.pl, linux-gpio@...r.kernel.org,
        linux-kernel@...r.kernel.org, palmer@...belt.com, maz@...nel.org,
        Daire.McNamara@...rochip.com
Subject: Re: [PATCH v6 1/1] gpio: mpfs: add polarfire soc gpio support

On Tue, Aug 30, 2022 at 6:51 AM <Lewis.Hanly@...rochip.com> wrote:

> We had looked at the bpgpio_init, our controller is not fully memory
> mapped to support the bgpio_init() and get all routines for free.
> While we have in/out and intr (interrupt state) 32-bit registers, we
> would not get as much free as other generic memory mapped controllers.

You're not really saying what the problem is?

Is it that some registers are not one-bit-indexed from 0 per GPIO?

Yours,
Linus Walleij

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