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Message-ID: <f16cbcaa-1457-b809-1323-39f07695bc7c@linaro.org>
Date:   Thu, 1 Sep 2022 18:29:16 +0300
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Rajendra Nayak <quic_rjendra@...cinc.com>, agross@...nel.org,
        andersson@...nel.org, konrad.dybcio@...ainline.org,
        robh+dt@...nel.org
Cc:     linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH 3/4] soc: qcom: icc-bwmon: force clear counter/irq
 registers

On 01/09/2022 15:47, Rajendra Nayak wrote:
> In some SoCs we have to force clear the counter/irq clear registers as
> they are not self clearing after they are written into.
> sc7280 seems to be one such SoC, handle this with a quirk flag.
> 
> Signed-off-by: Rajendra Nayak <quic_rjendra@...cinc.com>


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>


Best regards,
Krzysztof

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