linux-kernel - Re: [PATCH 06/14] arm64: dts: qcom: sm6115: Add usb and related phy nodes

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Message-ID: <8b1f1576-62c1-5a17-561a-619b88587a4a@linaro.org>
Date:   Thu, 1 Sep 2022 19:06:19 +0300
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Iskren Chernev <iskren.chernev@...il.com>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>
Cc:     phone-devel@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        Andy Gross <agross@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...ainline.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 06/14] arm64: dts: qcom: sm6115: Add usb and related phy
 nodes

On 01/09/2022 10:24, Iskren Chernev wrote:
> Add support for the USB controller and its HS PHY to SM6115.
> 
> Signed-off-by: Iskren Chernev <iskren.chernev@...il.com>
> ---
>  arch/arm64/boot/dts/qcom/sm6115.dtsi | 62 ++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index a6be8b93a44d..00fd185c87aa 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -412,6 +412,21 @@ gcc: clock-controller@...0000 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		hsusb_phy: phy@...3000 {
> +			compatible = "qcom,sm6115-qusb2-phy";
> +			reg = <0x1613000 0x180>;
> +			#phy-cells = <0>;
> +
> +			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> +				 <&gcc GCC_AHB2PHY_USB_CLK>;
> +			clock-names = "ref", "cfg_ahb";
> +
> +			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> +			nvmem-cells = <&qusb2_hstx_trim>;
> +
> +			status = "disabled";
> +		};
> +
>  		qfprom@...0000 {
>  			compatible = "qcom,qfprom";
>  			reg = <0x1b40000 0x7000>;
> @@ -434,6 +449,53 @@ rpm_msg_ram: memory@...0000 {
>  			reg = <0x45f0000 0x7000>;
>  		};
>  
> +		usb3: usb@...8800 {
> +			compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
> +			reg = <0x04ef8800 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> +				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> +				 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
> +				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> +				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> +				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
> +			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
> +				      "sleep", "xo";
> +
> +			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> +					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> +			assigned-clock-rates = <19200000>, <66666667>;
> +
> +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hs_phy_irq", "ss_phy_irq";
> +
> +			resets = <&gcc GCC_USB30_PRIM_BCR>;
> +			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
> +			qcom,select-utmi-as-pipe-clk;
> +			status = "disabled";
> +
> +			usb3_dwc3: dwc3@...0000 {

Node name: usb

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

Best regards,
Krzysztof