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Date: Thu, 1 Sep 2022 12:02:34 +0800 From: Richard Zhu <hongxing.zhu@....com> To: p.zabel@...gutronix.de, l.stach@...gutronix.de, bhelgaas@...gle.com, lorenzo.pieralisi@....com, robh@...nel.org, shawnguo@...nel.org, vkoul@...nel.org, alexander.stein@...tq-group.com, marex@...x.de, richard.leitner@...ux.dev Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org, linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, kernel@...gutronix.de, linux-imx@....com, Richard Zhu <hongxing.zhu@....com> Subject: [PATCH v6 1/7] dt-binding: phy: Add iMX8MP PCIe PHY binding Add i.MX8MP PCIe PHY binding. On iMX8MM, the initialized default value of PERST bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1. But i.MX8MP has one inversed default value 1b'0 of PERST bit. And the PERST bit should be kept 1b'1 after power and clocks are stable. So add one more PERST explicitly for i.MX8MP PCIe PHY. Signed-off-by: Richard Zhu <hongxing.zhu@....com> Tested-by: Marek Vasut <marex@...x.de> Tested-by: Richard Leitner <richard.leitner@...data.com> Tested-by: Alexander Stein <alexander.stein@...tq-group.com> --- .../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml index b6421eedece3..692783c7fd69 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - fsl,imx8mm-pcie-phy + - fsl,imx8mp-pcie-phy reg: maxItems: 1 @@ -28,11 +29,16 @@ properties: - const: ref resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: - items: - - const: pciephy + oneOf: + - items: # for iMX8MM + - const: pciephy + - items: # for IMX8MP + - const: pciephy + - const: perst fsl,refclk-pad-mode: description: | @@ -60,6 +66,10 @@ properties: description: A boolean property indicating the CLKREQ# signal is not supported in the board design (optional) + power-domains: + description: PCIe PHY power domain (optional). + maxItems: 1 + required: - "#phy-cells" - compatible -- 2.25.1
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