linux-kernel - RE: [PATCH v5 5/7] soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets

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Message-ID: <AS8PR04MB86765B884C1CAA5B7441A72F8C7B9@AS8PR04MB8676.eurprd04.prod.outlook.com>
Date:   Thu, 1 Sep 2022 01:28:13 +0000
From:   Hongxing Zhu <hongxing.zhu@....com>
To:     Lucas Stach <l.stach@...gutronix.de>,
        "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "robh@...nel.org" <robh@...nel.org>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "vkoul@...nel.org" <vkoul@...nel.org>,
        "alexander.stein@...tq-group.com" <alexander.stein@...tq-group.com>,
        "marex@...x.de" <marex@...x.de>,
        "richard.leitner@...ux.dev" <richard.leitner@...ux.dev>
CC:     "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH v5 5/7] soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets

> -----Original Message-----
> From: Lucas Stach <l.stach@...gutronix.de>
> Sent: 2022年8月31日 16:37
> To: Hongxing Zhu <hongxing.zhu@....com>; p.zabel@...gutronix.de;
> bhelgaas@...gle.com; lorenzo.pieralisi@....com; robh@...nel.org;
> shawnguo@...nel.org; vkoul@...nel.org; alexander.stein@...tq-group.com;
> marex@...x.de; richard.leitner@...ux.dev
> Cc: linux-phy@...ts.infradead.org; devicetree@...r.kernel.org;
> linux-pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> linux-kernel@...r.kernel.org; kernel@...gutronix.de; dl-linux-imx
> <linux-imx@....com>
> Subject: Re: [PATCH v5 5/7] soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets
> 
> Am Dienstag, dem 30.08.2022 um 15:46 +0800 schrieb Richard Zhu:
> > From: Lucas Stach <l.stach@...gutronix.de>
> >
> > Dessert the PHY reset when powering up the domain and put it back into
> > reset when the domain is powered down.
> >
> > Signed-off-by: Lucas Stach <l.stach@...gutronix.de>
> 
> According to patch submission guidelines you need to add your own sign- off
> when integrating this patch into your series. Please add in the next revision.

Okay, thanks.

Best Regards
Richard Zhu
> 
> Regards,
> Lucas
> 
> > ---
> >  drivers/soc/imx/imx8mp-blk-ctrl.c | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c
> > b/drivers/soc/imx/imx8mp-blk-ctrl.c
> > index 4ca2ede6871b..6c939d68ba9a 100644
> > --- a/drivers/soc/imx/imx8mp-blk-ctrl.c
> > +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
> > @@ -18,6 +18,8 @@
> >  #define GPR_REG0		0x0
> >  #define  PCIE_CLOCK_MODULE_EN	BIT(0)
> >  #define  USB_CLOCK_MODULE_EN	BIT(1)
> > +#define  PCIE_PHY_APB_RST	BIT(4)
> > +#define  PCIE_PHY_INIT_RST	BIT(5)
> >
> >  struct imx8mp_blk_ctrl_domain;
> >
> > @@ -75,6 +77,10 @@ static void imx8mp_hsio_blk_ctrl_power_on(struct
> imx8mp_blk_ctrl *bc,
> >  	case IMX8MP_HSIOBLK_PD_PCIE:
> >  		regmap_set_bits(bc->regmap, GPR_REG0,
> PCIE_CLOCK_MODULE_EN);
> >  		break;
> > +	case IMX8MP_HSIOBLK_PD_PCIE_PHY:
> > +		regmap_set_bits(bc->regmap, GPR_REG0,
> > +				PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
> > +		break;
> >  	default:
> >  		break;
> >  	}
> > @@ -90,6 +96,10 @@ static void imx8mp_hsio_blk_ctrl_power_off(struct
> imx8mp_blk_ctrl *bc,
> >  	case IMX8MP_HSIOBLK_PD_PCIE:
> >  		regmap_clear_bits(bc->regmap, GPR_REG0,
> PCIE_CLOCK_MODULE_EN);
> >  		break;
> > +	case IMX8MP_HSIOBLK_PD_PCIE_PHY:
> > +		regmap_clear_bits(bc->regmap, GPR_REG0,
> > +				  PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
> > +		break;
> >  	default:
> >  		break;
> >  	}
>