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Date: Thu, 1 Sep 2022 13:46:36 +0300 From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org> To: Philipp Zabel <p.zabel@...gutronix.de>, Akhil P Oommen <quic_akhilpo@...cinc.com> Cc: freedreno <freedreno@...ts.freedesktop.org>, dri-devel@...ts.freedesktop.org, linux-arm-msm@...r.kernel.org, Rob Clark <robdclark@...il.com>, Bjorn Andersson <bjorn.andersson@...aro.org>, Stephen Boyd <swboyd@...omium.org>, Douglas Anderson <dianders@...omium.org>, krzysztof.kozlowski@...aro.org, Andy Gross <agross@...nel.org>, Konrad Dybcio <konrad.dybcio@...ainline.org>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH v6 4/6] clk: qcom: gpucc-sc7280: Add cx collapse reset support On 01/09/2022 13:34, Philipp Zabel wrote: > On Wed, Aug 31, 2022 at 10:48:25AM +0530, Akhil P Oommen wrote: >> Allow a consumer driver to poll for cx gdsc collapse through Reset >> framework. >> >> Signed-off-by: Akhil P Oommen <quic_akhilpo@...cinc.com> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org> >> --- >> >> (no changes since v3) >> >> Changes in v3: >> - Convert 'struct qcom_reset_ops cx_gdsc_reset' to 'static const' (Krzysztof) >> >> Changes in v2: >> - Minor update to use the updated custom reset ops implementation >> >> drivers/clk/qcom/gpucc-sc7280.c | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c >> index 9a832f2..fece3f4 100644 >> --- a/drivers/clk/qcom/gpucc-sc7280.c >> +++ b/drivers/clk/qcom/gpucc-sc7280.c >> @@ -433,12 +433,22 @@ static const struct regmap_config gpu_cc_sc7280_regmap_config = { >> .fast_io = true, >> }; >> >> +static const struct qcom_reset_ops cx_gdsc_reset = { >> + .reset = gdsc_wait_for_collapse, > > This should be accompanied by a comment explaining the not-quite-reset > nature of this workaround, i.e. what is the prerequisite for this to > actually work as expected? > >> +}; >> + >> +static const struct qcom_reset_map gpucc_sc7280_resets[] = { >> + [GPU_CX_COLLAPSE] = { .ops = &cx_gdsc_reset, .priv = &cx_gdsc }, >> +}; >> + >> static const struct qcom_cc_desc gpu_cc_sc7280_desc = { >> .config = &gpu_cc_sc7280_regmap_config, >> .clks = gpu_cc_sc7280_clocks, >> .num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks), >> .gdscs = gpu_cc_sc7180_gdscs, >> .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs), >> + .resets = gpucc_sc7280_resets, >> + .num_resets = ARRAY_SIZE(gpucc_sc7280_resets), > > See my comment on patch 2. I think instead of adding a const struct > qcom_reset_ops * to gpucc_sc7280_resets, this should just add a const > struct reset_control * to gpu_cc_sc7280_desc. While this will work for the sc7280, the platform that Akhil was developing, this will not work for other platforms (like sm8250), where the dispcc also provides traditional BCR resets. -- With best wishes Dmitry
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