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Message-ID: <20220901133403.3392291-3-conor.dooley@microchip.com>
Date: Thu, 1 Sep 2022 14:33:57 +0100
From: Conor Dooley <conor.dooley@...rochip.com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor.dooley@...rochip.com>,
Daire McNamara <daire.mcnamara@...rochip.com>,
Shravan Chippa <shravan.chippa@...rochip.com>
CC: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Cyril Jean <Cyril.Jean@...rochip.com>,
Lewis Hanly <lewis.hanly@...rochip.com>,
Vattipalli Praveen <praveen.kumar@...rochip.com>,
Wolfgang Grandegger <wg@...es-embedded.de>,
Hugh Breslin <hugh.breslin@...rochip.com>,
<devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH v3 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp
Add a compatible for the Aries Embedded M100PFSEVP SOM + EVK platform.
Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 485981fbfb4b..630f82c85a0c 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -27,6 +27,7 @@ properties:
- items:
- enum:
+ - aries,m100pfsevp
- sundance,polarberry
- const: microchip,mpfs
--
2.36.1
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