linux-kernel - Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

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Message-ID: <20220902193650.GA285986-robh@kernel.org>
Date:   Fri, 2 Sep 2022 14:36:50 -0500
From:   Rob Herring <robh@...nel.org>
To:     Ben Dooks <ben.dooks@...ive.com>
Cc:     robh+dt@...nel.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, conor.dooley@...rochip.com,
        krzysztof.kozlowski+dt@...aro.org, devicetree@...r.kernel.org,
        palmer@...belt.com, paul.walmsley@...ive.com,
        greentime.hu@...ive.com, aou@...s.berkeley.edu
Subject: Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for
 l3 cache

On Tue, 30 Aug 2022 13:51:33 +0100, Ben Dooks wrote:
> With newer cores such as the p550, the SiFive composable cache can be
> a level 3 cache. Update the cache level to be one of 2 or 3.
> 
> Signed-off-by: Ben Dooks <ben.dooks@...ive.com>
> ---
>  Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@...nel.org>