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Date:   Sat, 3 Sep 2022 02:03:53 +0300
From:   Serge Semin <fancer.lancer@...il.com>
To:     Sudip Mukherjee <sudip.mukherjee@...ive.com>
Cc:     Serge Semin <Sergey.Semin@...kalelectronics.ru>,
        Mark Brown <broonie@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Greentime Hu <greentime.hu@...ive.com>,
        Jude Onyenegecha <jude.onyenegecha@...ive.com>,
        William Salmon <william.salmon@...ive.com>,
        Adnan Chowdhury <adnan.chowdhury@...ive.com>,
        Ben Dooks <ben.dooks@...ive.com>, linux-spi@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Jeegar Lakhani <jeegar.lakhani@...ive.com>
Subject: Re: [PATCH 00/11] Add support for enhanced SPI for Designware SPI
 controllers

On Tue, Aug 30, 2022 at 09:48:35AM +0100, Sudip Mukherjee wrote:
> On Fri, Aug 26, 2022 at 7:03 PM Serge Semin <fancer.lancer@...il.com> wrote:
> >
> > Hello Sudip
> >
> > On Tue, Aug 02, 2022 at 06:57:44PM +0100, Sudip Mukherjee wrote:
> > > Some Synopsys SSI controllers support enhanced SPI which includes
> > > Dual mode, Quad mode and Octal mode. DWC_ssi includes clock stretching
> > > feature in enhanced SPI modes which can be used to prevent FIFO underflow
> > > and overflow conditions while transmitting or receiving the data respectively.
> > > This is only tested on controller version 1.03a.
> >
> 
> <snip>
> 
> >
> > I've deliberately collected all the generic comments here so you'd be
> > aware of the required changes in total, because I very much doubt all
> > of them could be fixed at once via a single patchset iteration. But as
> > soon as all of them are fixed we'll get a very nice and neat solution
> > for the eSPI feature.
> >
> 

> Thanks a lot for the summary here Sergey. I am sure I will have a few
> questions for you after I start with the changes.

Ok. Don't hesitate to ask.

-Sergey

> 
> -- 
> Regards
> Sudip

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